JAJSMA5C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics: Wide Bandwidth Mode

at TA = 25°C, VS = ±6V, RL = 100 Ω || 400 fF, RS = 25 Ω, VOCM = 0V (mid-supply), CLH and CLL tied to VS+ and VS– respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ)
PARAMETER Test Condition MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-Signal Bandwidth VOUT = 100 mVPP 3.1 GHz
LSBW Large-Signal Bandwidth  VOUT = 1 VPP 3.1
VOUT = 2 VPP 1.6
Bandwidth for 0.1 dB flatness VOUT = 1 VPP 0.6
Bandwidth for -1 dB flatness 1.8
Bandwidth for -2 dB flatness RL = 50 Ω 2.4
SR Slew rate VOUT = 1.2-V step, VIN-SR = 13000 V/µs 7000 V/µs
Rise and fall time VOUT = 1.2-V step (10% to 90%) 0.16 ns
VOUT = 0.25-V step (10% to 90%) 0.15
Settling time to 0.1% VOUT = 1.2-V step, VIN-SR = 13000 V/µs 1.3 ns
Settling time to 1% 0.7
en Voltage noise 1/f corner 18 kHz
f = 100 MHz in BF Mode and CL Mode 2.3 nV/√Hz
in Current noise f = 10 kHz 1.5 pA/√Hz
HD2/HD3 Harmonic distortion VOUT = 2 VPP f = 500 MHz –68/–58 dBc
VOUT = 1 VPP f = 1 GHz –55/–59
f = 2 GHz –45/–49
f = 2 GHz, RL = 50 Ω –43/–41
DC PERFORMANCE
VOS Input offset voltage VOUT – VIN –600 –800 mV
TA = –40℃ to 85℃ –900
dVOS/dT Input offset voltage drift TA = –40℃ to 85℃ ±700 ±1330 µV/℃
IB Input bias current 3 25 pA
TA = –40℃ to 85℃ 220
IAB Auxiliary Input bias current 44 140 µA
TA = –40℃ to 85℃ 200
G DC Gain VOUT = ± 0.5 V RL = 200 Ω  0.97 0.978 0.99 V/V
RL = 100 Ω 0.96 0.971 0.98
RL = 50 Ω 0.95 0.961 0.97
VOUT = ± 0.5 V ,TA = –40℃ to 85℃ RL = 200 Ω 0.97 0.99
RL = 100 Ω 0.96 0.98
RL = 50 Ω 0.94 0.97
INPUT
ZIN Input impedance f = 100 MHz  50 || 2.4 GΩ || pF
Input Clamp current rating Continous Current Rating 100 mA
VCLH range(1) 0 VS+ V
VCLL range(1) VS– 0
CLH Clamping Time Time taken to clamp VOUT to VCLH during overdrive 0.2 nsec
CLL Clamping Time Time taken to clamp VOUT to VCLL during overdrive 0.2
Input Voltage Range THD = – 40 dBc f = 500 MHz 4.5 VPP
f = 1 GHz 2.1
f = 2 GHz 1.2
OUTPUT
Output Swing TA = 25℃ VS+ – 1.9 V
VS– + 3.4
TA = –40℃ to 85℃ VS+ – 2.0
VS– + 3.4
ZO Output impedance f = 100 MHz 1.2 Ω
AUXILIARY INPUT
GAUX VOUT  to In_Aux Gain  0.18 0.26 V/V
TA = –40℃ to 85℃ 0.23 V/V
Default voltage at In_Aux VS– + 2.3 VS– + 3 VS– + 3.8 V
In_Aux Input Voltage Range  VS– + 1.0 VS– + 5.0 V
VOUT to In_Aux  Bandwidth  800 MHz
RHF Resistance between In_Bias to JFET source 100 kΩ
POWER SUPPLY
VS Operating voltage range ±4.5 ±6.5 V
IQ Quiescent current IOUT = 0 (R_bias = 17.8 kΩ)  34 37 mA
TA = –40℃ to 85℃ 35.5
CL Mode enabled 36 40
PSRR Power-supply rejection ratio PSRR at 100 kHz on VS+ 49 dB
PSRR at 100 kHz on VS– 38
(1) The 0-V limits are for bipolar and balanced power supplies. For other supply configurations mid-supply will set the minimum limit for VCLH and maximum limit for VCLL