JAJSMA5C June   2021  – March 2022 BUF802

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Wide Bandwidth Mode
    6. 6.6 Electrical Characteristics: Low Quiescent Current Mode
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and Output Over-Voltage Clamp
      2. 8.3.2 Adjustable Quiescent Current
      3. 8.3.3 ESD Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buffer Mode (BF Mode)
      2. 8.4.2 Composite Loop Mode (CL Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Oscilloscope Front-End Amplifier Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance
        1. 9.2.2.1 Detailed Design Results
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics: Low Quiescent Current Mode

at TA = 25°C, VS = ±6 V, RL = 100 Ω || 400 fF.  RS = 25 Ω, VOCM = 0 V (mid-supply), CLH and CLL tied to VS+ and VS– respectively, Low Quiescent Current Mode unless otherwise specified (R_Bias = 35.7 kΩ)
PARAMETER Test Condition MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-Signal Bandwidth VOUT = 100 mVPP 2.6 GHz
LSBW Large-Signal Bandwidth  VOUT = 1 VPP 2
VOUT = 2 VPP 0.7
Bandwidth for 0.1 dB flatness VOUT = 1 VPP 0.45
Bandwidth for -1 dB flatness 1.4
SR Slew rate VOUT  = 1.2-V step, VIN-SR = 13000 V/µs 5500 V/µs
Rise and fall time VOUT  = 1.2-V step (10% to 90%) 0.3 ns
VOUT  = 0.25-V step (10% to 90%) 0.16
Settling time to 0.1% VOUT  = 1.2-V step, VIN-SR = 13000 V/µs 1.4 ns
Settling time to 1% 0.8
en Voltage noise 1/f corner 10 kHz
f = 100 MHz 2.2 nV/√Hz
in Current noise f = 10 kHz 1.5 pA/√Hz
HD2/HD3 Harmonic distortion VOUT = 2 VPP f = 500 MHz –35/–32 dBc
VOUT = 1 VPP f = 100 MHz –80/–77
f = 500 MHz –56/–54
DC PERFORMANCE
G DC Gain VOUT = ± 0.5 V RL = 200 Ω  0.96 0.975 0.99 V/V
RL = 100 Ω 0.95 0.963 0.98
VOUT = ± 0.5 V ,TA = –40℃ to 85℃ RL = 200 Ω 0.96 0.99
RL = 100 Ω 0.95 0.98
INPUT
CLH Clamping Time Time taken to clamp VOUT to VCLH during overdrive 0.3 nsec
CLL Clamping Time Time taken to clamp VOUT to VCLL during overdrive 0.7
OUTPUT
ZO Output impedance f = 100 MHz 1.2 Ω
POWER SUPPLY
VS Operating voltage range ±4.5 ±6.5 V
IQ Quiescent current IOUT = 0 (R_bias = 35.7 kΩ)  21 24 mA
TA = –40℃ to 85℃ 22