SWRS046I November   2006  – September 2018 CC1020

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Configuration
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  RF Transmit
    5. 4.5  RF Receive
    6. 4.6  RSSI / Carrier Sense
    7. 4.7  Intermediate Frequency (IF)
    8. 4.8  Crystal Oscillator
    9. 4.9  Frequency Synthesizer
    10. 4.10 Digital Inputs and Outputs
    11. 4.11 Current Consumption
    12. 4.12 Thermal Resistance Characteristics for VQFNP Package
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
      1. 5.3.1 Configuration Software
    4. 5.4  Microcontroller Interface
      1. 5.4.1 Configuration Interface
      2. 5.4.2 Signal Interface
      3. 5.4.3 PLL Lock Signal
    5. 5.5  4-wire Serial Configuration Interface
    6. 5.6  Signal Interface
      1. 5.6.1 Synchronous NRZ Mode
      2. 5.6.2 Transparent Asynchronous UART Mode
      3. 5.6.3 Synchronous Manchester Encoded Mode
        1. 5.6.3.1 Manchester Encoding and Decoding
    7. 5.7  Data Rate Programming
    8. 5.8  Frequency Programming
      1. 5.8.1 Dithering
    9. 5.9  Receiver
      1. 5.9.1  IF Frequency
      2. 5.9.2  Receiver Channel Filter Bandwidth
      3. 5.9.3  Demodulator, Bit Synchronizer, and Data Decision
      4. 5.9.4  Receiver Sensitivity Versus Data Rate and Frequency Separation
      5. 5.9.5  RSSI
      6. 5.9.6  Image Rejection Calibration
      7. 5.9.7  Blocking and Selectivity
      8. 5.9.8  Linear IF Chain and AGC Settings
      9. 5.9.9  AGC Settling
      10. 5.9.10 Preamble Length and Sync Word
      11. 5.9.11 Carrier Sense
      12. 5.9.12 Automatic Power-up Sequencing
      13. 5.9.13 Automatic Frequency Control
      14. 5.9.14 Digital FM
    10. 5.10 Transmitter
      1. 5.10.1 FSK Modulation Formats
      2. 5.10.2 Output Power Programming
      3. 5.10.3 TX Data Latency
      4. 5.10.4 Reducing Spurious Emission and Modulation Bandwidth
    11. 5.11 Input and Output Matching and Filtering
    12. 5.12 Frequency Synthesizer
      1. 5.12.1 VCO, Charge Pump and PLL Loop Filter
      2. 5.12.2 VCO and PLL Self-Calibration
      3. 5.12.3 PLL Turn-on Time Versus Loop Filter Bandwidth
      4. 5.12.4 PLL Lock Time Versus Loop Filter Bandwidth
    13. 5.13 VCO and LNA Current Control
    14. 5.14 Power Management
    15. 5.15 On-Off Keying (OOK)
    16. 5.16 Crystal Oscillator
    17. 5.17 Built-in Test Pattern Generator
    18. 5.18 Interrupt on Pin DCLK
      1. 5.18.1 Interrupt Upon PLL Lock
      2. 5.18.2 Interrupt Upon Received Signal Carrier Sense
    19. 5.19 PA_EN and LNA_EN Digital Output Pins
      1. 5.19.1 Interfacing an External LNA or PA
      2. 5.19.2 General Purpose Output Control Pins
      3. 5.19.3 PA_EN and LNA_EN Pin Drive
    20. 5.20 System Considerations and Guidelines
      1. 5.20.1 SRD Regulations
      2. 5.20.2 Narrowband Systems
      3. 5.20.3 Low Cost Systems
      4. 5.20.4 Battery Operated Systems
      5. 5.20.5 High Reliability Systems
      6. 5.20.6 Frequency Hopping Spread Spectrum Systems (FHSS)
    21. 5.21 Antenna Considerations
    22. 5.22 Configuration Registers
      1. 5.22.1 Memory
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
    2. 6.2 Design Requirements
      1. 6.2.1 Input and Output Matching
      2. 6.2.2 Bias Resistor
      3. 6.2.3 PLL Loop Filter
      4. 6.2.4 Crystal
      5. 6.2.5 Additional Filtering
      6. 6.2.6 Power Supply Decoupling and Filtering
    3. 6.3 PCB Layout Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

4.4 RF Transmit

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V,
fC = 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Transmit data rate 0.45 153.6 kBaud The data rate is programmable. See Section 5.7 for details.
NRZ or Manchester encoding can be used. 153.6 kBaud equals 153.6 kbps using NRZ coding and 76.8 kbps using Manchester coding. See Section 5.4.2 for details.
Minimum data rate for OOK is 2.4 kBaud
Binary FSK frequency separation in 402 to 470 MHz range 0 108 kHz 108/216 kHz is the maximum specified separation at 1.84 MHz reference frequency. Larger separations can be achieved at higher reference frequencies.
in 804 to 930 MHz range 0 216 kHz
Output power 433 MHz –20 to +10 dBm Delivered to 50 Ω single-ended load. The output power is programmable and should not be programmed to exceed +10/+5 dBm at 433/868 MHz under any operating conditions (refer to CC1020 Errata Note 003 in the CC1020 product folder). See Section 5.11 for details.
868 MHz –20 to +5 dBm
Output power tolerance At 2.3 V, +85°C –4 dB At maximum output power
At 3.6 V, –40°C 3 dB
Harmonics, radiated CW 2nd harmonic, 433 MHz,
+10 dBm		 –50 dBc Harmonics are measured as EIRP values according to EN 300 220. The antenna (SMAFF-433 and SMAFF-868 from R.W. Badland) plays a part in attenuating the harmonics.
3rd harmonic, 433 MHz,
+10 dBm		 –50 dBc
2nd harmonic, 868 MHz,
+5 dBm		 –50 dBc
3rd harmonic, 868 MHz,
+5 dBm		 –50 dBc
Adjacent channel power (GFSK) 12.5 kHz channel spacing,
433 MHz		 –46 dBc For 12.5 kHz channel spacing ACP is measured in a ±4.25 kHz bandwidth at ±12.5 kHz offset. Modulation: 2.4 kBaud NRZ PN9 sequence, ±2.025 kHz frequency deviation.
For 25 kHz channel spacing ACP is measured in a ±8.5 kHz bandwidth at ±25 kHz offset. Modulation: 4.8 kBaud NRZ PN9 sequence, ±2.475 kHz frequency deviation.
25 kHz channel spacing,
433 MHz		 –52 dBc
25 kHz channel spacing,
868 MHz		 –49 dBc
Occupied bandwidth (99.5%,GFSK) 12.5 kHz channel spacing,
433 MHz		 7.5 kHz Bandwidth for 99.5% of total average power.
Modulation for 12.5 channel spacing:
2.4 kBaud NRZ PN9 sequence,
±2.025 kHz frequency deviation.
Modulation for 25 kHz channel spacing: 4.8 kBaud NRZ PN9 sequence,
±2.475 kHz frequency deviation.
25 kHz channel spacing,
433 MHz		 9.6 kHz
25 kHz channel spacing,
868 MHz		 9.6 kHz
Modulation bandwidth,
868 MHz		 19.2 kBaud, ±9.9 kHz frequency deviation 48 kHz Bandwidth where the power envelope of modulation equals –36 dBm. Spectrum analyzer
RBW = 1 kHz.
38.4 kBaud, ±19.8 kHz frequency deviation 106 kHz
Spurious emission, radiated CW 47 to 74, 87.5 to 118, 174 to 230, 470 to 862 MHz –54 dBm At maximum output power, +10/+5 dBm at 433/868 MHz.
To comply with EN 300 220 and FCC CFR47 part 15 an external (antenna) filter, as implemented in the application circuit in Section 5.11, must be used and tailored to each individual design to reduce out-of-band spurious emission levels.
Spurious emissions can be measured as EIRP values according to EN 300 220. The antenna (SMAFF-433 and SMAFF-868 from R.W. Badland) plays a part in attenuating the spurious emissions.
If the output power is increased using an external PA, a filter must be used to attenuate spurs below 862 MHz when operating in the 868 MHz frequency band in Europe. Application Note AN036 CC1020/1021 Reducing Spurious Emission (SWRA057) presents and discusses a solution that reduces the TX mode spurious emission close to 862 MHz by increasing the REF_DIV from 1 to 7.
9 kHz to 1 GHz –36 dBm
1 to 4 GHz –30 dBm
Optimum load impedance 433 MHz 54 + j44 Ω Transmit mode. For matching details see Section 5.11.
868 MHz 15 + j24 Ω
915 MHz 20 + j35 Ω