SWRS112H June   2011  – July 2015 CC1120

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Configuration
  4. 4Specifications
    1. 4.1  ESD Ratings
    2. 4.2  Recommended Operating Conditions (General Characteristics)
    3. 4.3  RF Characteristics
    4. 4.4  Power Consumption Summary
    5. 4.5  Receive Parameters
    6. 4.6  Transmit Parameters
    7. 4.7  PLL Parameters
    8. 4.8  32-MHz Clock Input (TCXO)
    9. 4.9  32-MHz Crystal Oscillator
    10. 4.10 32-kHz Clock Input
    11. 4.11 32-kHz RC Oscillator
    12. 4.12 I/O and Reset
    13. 4.13 Temperature Sensor
    14. 4.14 Thermal Resistance Characteristics for RHB Package
    15. 4.15 Timing Requirements
    16. 4.16 Regulatory Standards
    17. 4.17 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Block Diagram
    2. 5.2 Frequency Synthesizer
    3. 5.3 Receiver
    4. 5.4 Transmitter
    5. 5.5 Radio Control and User Interface
    6. 5.6 Enhanced Wake-On-Radio (eWOR)
    7. 5.7 Sniff Mode
    8. 5.8 Antenna Diversity
    9. 5.9 WaveMatch
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application Circuit
      2. 6.1.2 TI Reference Designs
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Configuration Software
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical Packaging and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Terminal Configuration and Functions

3.1 Pin Diagram

Figure 3-1 shows pin names and locations for the CC1120 device.

CC1120 po_swrs112.gifFigure 3-1 Package 5-mm × 5-mm QFN

3.2 Pin Configuration

The following table lists the pinout configuration for the CC1120 device.

PIN TYPE DESCRIPTION
NO. NAME
1 VDD_GUARD Power 2.0–3.6 V VDD
2 RESET_N Digital input Asynchronous, active-low digital reset
3 GPIO3 Digital I/O General-purpose I/O
4 GPIO2 Digital I/O General-purpose I/O
5 DVDD Power 2.0–3.6 VDD to internal digital regulator
6 DCPL Power Digital regulator output to external decoupling capacitor
7 SI Digital input Serial data in
8 SCLK Digital input Serial data clock
9 SO(GPIO1) Digital I/O Serial data out (general-purpose I/O)
10 GPIO0 Digital I/O General-purpose I/O
11 CSn Digital input Active-low chip select
12 DVDD Power 2.0–3.6 V VDD
13 AVDD_IF Power 2.0–3.6 V VDD
14 RBIAS Analog External high-precision resistor
15 AVDD_RF Power 2.0–3.6 V VDD
16 N.C. — Not connected
17 PA Analog Single-ended TX output (requires DC path to VDD)
18 TRX_SW Analog TX and RX switch. Connected internally to GND in TX and floating (high-impedance) in RX.
19 LNA_P Analog Differential RX input (requires DC path to ground)
20 LNA_N Analog Differential RX input (requires DC path to ground)
21 DCPL_VCO Power Pin for external decoupling of VCO supply regulator
22 AVDD_SYNTH1 Power 2.0–3.6 V VDD
23 LPF0 Analog External loop filter components
24 LPF1 Analog External loop filter components
25 AVDD_PFD_CHP Power 2.0–3.6 V VDD
26 DCPL_PFD_CHP Power Pin for external decoupling of PFD and CHP regulator
27 AVDD_SYNTH2 Power 2.0–3.6 V VDD
28 AVDD_XOSC Power 2.0–3.6 V VDD
29 DCPL_XOSC Power Pin for external decoupling of XOSC supply regulator
30 XOSC_Q1 Analog Crystal oscillator pin 1 (must be grounded if a TCXO or other external clock connected to EXT_XOSC is used)
31 XOSC_Q2 Analog Crystal oscillator pin 2 (must be left floating if a TCXO or other external clock connected to EXT_XOSC is used)
32 EXT_XOSC Digital input Pin for external clock input (must be grounded if a regular crystal connected to XOSC_Q1 and XOSC_Q2 is used)
— GND Ground pad The ground pad must be connected to a solid ground plane.