Table 5-1 SPI Interface Timing Requirements

5.5.1 Chip Status Byte

When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC115L on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running.

Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core are on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For these bits to give any valid information, the R/W bit in the header byte must be set to 0. The FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes can be written.

Table 5-2 gives a status byte summary.

5.5.2 Register Access

The configuration registers on the CC115L are located on SPI addresses from 0x00 to 0x2E. Table 5-14 lists all configuration registers. It is highly recommended to use SmartRF Studio SWRC176 to generate optimum register settings. The detailed description of each register is found in Section 5.19.1 and Section 5.19.2. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A₅ - A₀) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x30 - 0x3D, the burst bit is used to select between status registers when burst bit is one, and between command strobes when burst bit is zero (see Section 5.5.3). Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only be read.

5.5.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (that is, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC115L Errata Notes SWRZ037 for more details.

5.5.4 Command Strobes

Command Strobes may be viewed as single byte instructions to CC115L. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable transmit mode, enable calibration etc. The 11 command strobes are listed in Table 5-13.

The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit should be set to zero if the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES strobe is being issued, one will have to wait for SO to go low again before the next header byte can be issued as shown in Figure 5-4. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes, which are executed when CSn goes high.

Figure 5-4 SRES Command Strobe

5.5.5 TX FIFO Access

The 64-byte TX FIFO is accessed through the 0x3F address. The TX FIFO is write-only and the R/W bit should therefore be zero.

The burst bit is used to determine if the TX FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the FIFO:

• 0x3F: Single byte access to TX FIFO
• 0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte (see Section 5.5.1) is output on SO for each new data byte as shown in Figure 5-3. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that one byte is free in the TX FIFO.

The TX FIFO may be flushed by issuing a SFTX command strobe. A SFTX command strobe can only be issued in the IDLE, or TXFIFO_UNDERFLOW states. The TX FIFO is flushed when going to the SLEEP state.

Figure 5-5 gives a brief overview of different register access types possible.

5.5.6 PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects one or two data bytes after receiving the address (the burst bit must be set if two bytes are to be written). For OOK, two bytes should be written to PATABLE; the first byte after the address will set the logic 0 power level and the second byte written will set the logic 1 power level. For all other modulations formats, only one byte should be written to PATABLE. Use SmartRF Studio SWRC176 or DN013 SWRA168 for recommended register values for a given output power.

The PATABLE can also be read by setting the R/W bit to 1. The read operation can be done as a single byte or burst access, depending on how many bytes should be read (one or two). Note that pulling CSn high will reset the index counter to zero, meaning that burst access needs to be used for reading/writing the second PATABLE entry. For the same reason, if one byte is written to the PATABLE and this value is to be read out, CSn must be set high before the read access in order to set the index counter back to zero.

The content of the PATABLE is lost when entering the SLEEP state, except for the first byte, meaning that if OOK is used, the PATABLE needs to be reprogrammed when waking up from SLEEP.

Figure 5-5 Register Access Types

5.6.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK, and CSn). The SPI is described in Section 5.5.

5.6.2 General Control and Status Pins

The CC115L has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 5.16 for more details on the signals that can be programmed.

GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin.

In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode.

Table 5-3 Data Rate Step Size (Assuming a 26-MHz Crystal)

5.8.1 Packet Format

The format of the data packet can be configured and consists of the following items (see Figure 5-6):

• Preamble
• Synchronization word
• Optional length byte
• Optional address byte
• Payload
• Optional 2 byte CRC

Figure 5-6 Packet Format

The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum length of the preamble is programmable through the value of MDMCFG1.NUM_PREAMBLE. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is written to the TX FIFO. The modulator will then send the sync word and then the data bytes.

The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. If the CC110L, CC113L, or CC1101 are used at the receiving end, they will need the sync word for byte synchronization of the incoming packet. The synchronization word is automatically inserted by the CC115L. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by setting MDMCFG2.SYNC_MODE to 3. The sync word will then be repeated twice.

CC115L supports both constant packet length protocols and variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.

Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. This value must be different from 0.

In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte transmitted after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional CRC. The PKTLEN value must be different from 0.

With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission will continue until turned off manually. As described in , this can be used to support packet formats with different length configuration than natively supported by CC115L. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the CC115L Errata Notes SWRZ036 for more details.

5.8.1.1 Packet Length > 255

The packet automation control register, PKTCTRL0, can be reprogrammed during TX. This opens the possibility to transmit packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode (PKTCTRL0.LENGTH_CONFIG=2) must be active and the PKTLEN register is set to mod(length, 256). When less than 256 bytes remains of the packet, the MCU disables infinite packet length mode and activates fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). When the internal byte counter reaches the PKTLEN value, the transmission ends (the radio enters the state determined by TXOFF_MODE). Automatic CRC appending/checking can also be used (by setting PKTCTRL0.CRC_EN=1).

When for example a 600-byte packet is to be transmitted, the MCU should do the following (see Figure 5-7).

• Set PKTCTRL0.LENGTH_CONFIG=2.
• Pre-program the PKTLEN register to mod(600, 256) = 88.
• Transmit at least 345 bytes (600 - 255), for example by filling the 64-byte TX FIFO six times (384 bytes transmitted).
• Set PKTCTRL0.LENGTH_CONFIG=0.
• The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted.

Figure 5-7 Packet Length > 255

5.8.2 Packet Handling

The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If the receiver is the CC110L, CC113L, or CC1101, and address recognition is enabled, the second byte written to the TX FIFO must be the address byte.

If fixed packet length is enabled, the first byte written to the TX FIFO should be the address (assuming the receiver uses address recognition).

The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart TX mode.

5.8.3 Packet Handling in Firmware

When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been transmitted. Additionally, for packets longer than 64 bytes, the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be written to the TX FIFO. There are two possible solutions to get the necessary status information:

a. Interrupt Driven Solution

The GDO pins can be used to give an interrupt when a sync word has been transmitted or when a complete packet has been transmitted by setting IOCFGx.GDOx_CFG=0x06. In addition, there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that are in the TX FIFO (IOCFGx.GDOx_CFG=0x02 and IOCFGx.GDOx_CFG=0x03). See Table 5-12 for more information.

b. SPI Polling

The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The TXBYTES registers can be polled at a given rate to get information about the number of bytes in the and TX FIFO. Alternatively, the number of bytes in the TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus.

It is recommended to employ an interrupt driven solution due to a small, but finite, probability that a single read from registers PKTSTATUS and TXBYTES is being corrupt. The same is the case when reading the chip status byte (see Section 5.5.3 and the CC115L Errata Notes SWRZ036).

5.9.1 Frequency Shift Keying

CC115L supports 2-(G)FSK and 4-FSK modulation. When selecting 4-FSK, the preamble and sync word is sent using 2-FSK (see Figure 5-8).

The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by:

Equation 4.

The symbol encoding is shown in Table 5-4.

Figure 5-8 Data Sent Over the Air (MDMCFG2.MOD_FORMAT=100)

5.9.2 Amplitude Modulation

The amplitude modulation supported by CC115L is On-Off Keying (OOK). OOK modulation simply turns the PA on or off to modulate ones and zeros respectively.

The DEVIATN register setting has no effect when using OOK.

5.10.1 Power-On Start-Up Sequence

When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described below, that is, automatic power-on reset (POR) or manual reset. After the automatic power-on reset or manual reset, it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192. However, to optimize performance in TX, an alternative GDO setting from the settings found in Table 5-12 should be selected.

5.10.1.1 Automatic POR

A power-on reset circuit is included in the CC115L. The minimum requirements stated in Section 4.10 must be followed for the power-on reset to function properly. The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section 5.5.1 for more details on CHIP_RDYn.

When the CC115L reset is completed, the chip will be in the IDLE state and the crystal oscillator will be running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed, the SO pin will first go high, indicating that the crystal oscillator is not stabilized, before going low as shown in Figure 5-10.

Figure 5-10 Power-On Reset with SRES

5.10.1.2 Manual Reset

The other global reset possibility on CC115L uses the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual power-up sequence is as follows (see Figure 5-11):

• Set SCLK = 1 and SI = 0.
• Strobe CSn low / high.
• Hold CSn low and then high for at least 40 µs relative to pulling CSn low
• Pull CSn low and wait for SO to go low (CHIP_RDYn).
• Issue the SRES strobe on the SI line.
• When SO goes low again, reset is complete and the chip is in the IDLE state.

XOSC and voltage regulator switched on

Figure 5-11 Power-On Reset with SRES

NOTE

The above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC115L after this, it is only necessary to issue an SRES command strobe.

5.10.2 Crystal Control

The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ON is set.

In the automatic mode, the XOSC will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be used as described in Section 5.5.1.

If the XOSC is forced on, the crystal will always stay on even in the SLEEP state.

Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in Section 4.7.

5.10.3 Voltage Regulator Control

The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.

5.10.4 Transmit Mode (TX)

Transmit mode is activated directly by the MCU by using the STX command strobe.

The frequency synthesizer must be calibrated regularly. CC115L has one manual calibration option (using the SCAL strobe), and three automatic calibration options that are controlled by the MCSM0.FS_AUTOCAL setting:

• Calibrate when going from IDLE to TX (or FSTXON)
• Calibrate when going from TX to IDLE automatically (not forced in IDLE by issuing an SIDLE strobe)
• Calibrate every fourth time when going from TX to IDLE automatically (not forced in IDLE by issuing an SIDLE strobe)

If the radio goes from TX to IDLE by issuing an SIDLE strobe, calibration will not be performed. The calibration takes a constant number of XOSC cycles; see Table 5-5 for timing details regarding calibration.

When TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are:

• IDLE
• FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX
• TX: Start sending preamble

The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state.

5.10.5 Timing

Table 5-7 FIFO_THR Settings and the Corresponding FIFO Thresholds

5.13.1 VCO and PLL Self-Calibration

The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, CC115L includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 5-5.

The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode.

To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A, and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0, 1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC115L Errata Notes SWRZ037.

For more robust operation, the source code could include a check so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time.

Table 5-8 Optimum PATABLE Settings for Various Output Power Levels Using Wire-Wound Inductors in 868- and 915-MHz Frequency Bands

Table 5-9 Output Power and Current Consumption for Default PATABLE Setting Using Wire-Wound Inductors in 868- and 915-MHz Frequency Bands

Table 5-10 Optimum PATABLE Settings for Various Output Power Levels Using Multi-layer Inductors in 868- and 915-MHz Frequency Bands

Table 5-11 Output Power and Current Consumption for Default PATABLE Setting Using Multi-layer Inductors in 868- and 915-MHz Frequency Bands

Table 5-12 GDOx Signal Selection (x = 0, 1, or 2)

5.17.1 Asynchronous Serial Operation

Asynchronous transfer is included in the CC115L for backward compatibility with systems that are already using the asynchronous data transfer.

When asynchronous transfer is enabled, all packet handling support is disabled and it is not possible to use Manchester encoding.

Asynchronous serial mode is enabled by setting PKTCTRL0.PKT_FORMAT to 3. Strobing STX will configure the GDO0 pin as data input (TX data) regardless of the content of the IOCFG0 register. Data output can be on GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG fields.

The CC115L modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate.

5.17.2 Synchronous Serial Operation

Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync detection should be disabled together with CRC calculation (MDMCFG2.SYNC_MODE=000 and PKTCTRL0.CRC_EN=0). Infinite packet length mode should be used (PKTCTRL0.LENGTH_CONFIG=10b).

In synchronous serial mode, data is transferred on a two-wire serial interface. The CC115L provides a clock that is used to set up new data on the data input line or sample data on the data output line. Data input (TX data) is on the GDO0 pin. This pin will automatically be configured as an input when TX is active. The TX latency is 8 bits.

The MCU must handle preamble and sync word insertion/detection in software, together with CRC calculation and insertion.

5.18.1 SRD Regulations

International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands. The CC115L is specifically designed for such use with its 300–348 MHz, 387–464 MHz, and 779–928 MHz operating ranges. The most important regulations when using the CC115L in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 V2.3.1 (Europe) and FCC CFR47 Part 15 (USA).

For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26-MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.

Compliance with regulations is dependent on the complete system performance. It is the customer's responsibility to ensure that the system complies with regulations.

5.18.2 Calibration in Multi-Channel Systems

CC115L is highly suited for multi-channel systems due to its agile frequency synthesizer and effective communication interface.

Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing a multi-channel system. There are 3 ways of obtaining the calibration data from the chip:

1. Calibration for every frequency change. The PLL calibration time is 712/724 μs (26 MHz crystal and TEST0 = 0x09/0B, see Table 5-6). The blanking interval between each frequency hop is then 787/799 µs.
2. Perform all necessary calibration at startup and store the resulting FSCAL3, FSCAL2, and FSCAL1 register values in MCU memory. The VCO capacitance calibration FSCAL1 register value must be found for each RF frequency to be used. The VCO current calibration value and the charge pump current calibration value available in FSCAL2 and FSCAL3 respectively are not dependent on the RF frequency, so the same value can therefore be used for all RF frequencies for these two registers. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values that corresponds to the next RF frequency. The PLL turn on time is approximately 75 µs (see Table 5-5). The blanking interval between each frequency hop is then approximately 75 µs.
3. Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4], strobe STX with MCSM0.FS_AUTOCAL=1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done, but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from 712/724 µs to 145/157 µs (26 MHz crystal and TEST0 = 0x09/0B, see Table 5-6). The blanking interval between each frequency hop is then 220/232 µs.

There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. This solution also requires that the supply voltage and temperature do not vary much in order to have a robust solution. Solution 3) gives 567 µs smaller blanking interval than solution 1).

The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one should always use SmartRF Studio to get the correct settings for a specific frequency before doing a calibration, regardless of which calibration method is being used.

5.18.3 Wideband Modulation when not Using Spread Spectrum

Digital modulation systems under FCC Section 15.247 include 2-FSK, GFSK, and 4-FSK modulation. A maximum peak output power of 1 W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band.

Operating at high data rates and frequency separation, the CC115L is suited for systems targeting compliance with digital modulation system as defined by FCC Section 15.247. An external power amplifier such as CC1190 SWRS089 is needed to increase the output above +11 dBm. Refer to DN006 SWRA123 for further details concerning wideband modulation and CC115L.

5.18.4 Data Burst Transmissions

The high maximum data rate of CC115L opens up for burst transmissions. A low average data rate link (e.g. 10 kBaud) can be realized by using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kBaud) will reduce the time in TX mode, and hence also reduce the average current consumption significantly. Reducing the time in TX mode will reduce the likelihood of collisions with other systems in the same frequency range.

5.18.5 Continuous Transmissions

In data streaming applications, the CC115L opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some radios often prevents this kind of continuous data streaming and reduces the effective data rate).

5.18.6 Increasing Output Power

The PA portion of the CC1190 SWRS089 can be used together with CC115L in applications where increased output power is needed.

Table 5-13 Command Strobes

Table 5-14 Configuration Registers Overview

Table 5-15 Status Registers Overview

Table 5-16 SPI Address Space

5.19.1 Configuration Register Details - Registers with preserved values in SLEEP state

Table 5-27 0x0D: FREQ2 - Frequency Control Word, High Byte

Bit	Field Name	Reset	R/W	Description
7:6	FREQ[23:22]	0 (00)	R	FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26 - 27 MHz crystal)
5:0	FREQ[21:16]	30 (011110)	R/W	FREQ[23:0] is the base frequency for the frequency synthesizer in increments of fXOSC/216.

Table 5-31 0x11: MDMCFG3 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:0	DRATE_M[7:0]	34 (0x22)	R/W	The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden '1'. The resulting data rate is: The default values give a data rate of 115.051 kBaud (closest setting to 115.2 kBaud), assuming a 26.0 MHz crystal.

Table 5-34 0x14: MDMCFG0 - Modem Configuration

Bit	Field Name	Reset	R/W	Description
7:0	CHANSPC_M[7:0]	248 (0xF8)	R/W	8-bit mantissa of channel spacing. The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format: The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency.

Table 5-35 0x15: DEVIATN - Modem Deviation Setting

Bit	Field Name	Reset	R/W	Description
7			R0	Not used.
6:4	DEVIATION_E[2:0]	4 (100)	R/W	Deviation exponent.
3			R0	Not used.
2:0	DEVIATION_M[2:0]	7 (111)	R/W	2-FSK/GFSK/4-FSK	Specifies the nominal frequency deviation from the carrier for a '0' (-DEVIATN) and '1' (+DEVIATN) in a mantissa- exponent format, interpreted as a 4-bit value with MSB implicit 1. The resulting frequency deviation is given by: The default values give ±47.607 kHz deviation assuming 26.0 MHz crystal frequency.
				OOK	This setting has no effect

5.19.2 Configuration Register Details - Registers that Lose Programming in SLEEP State

5.19.3 Status Register Details