SWRS105B May   2011  – June 2014 CC115L

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  General Characteristics
    5. 4.5  Current Consumption
      1. 4.5.1 Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz
      2. 4.5.2 Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz
    6. 4.6  RF Transmit Section
      1. 4.6.1 Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz
      2. 4.6.2 Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz
    7. 4.7  Crystal Oscillator
    8. 4.8  Frequency Synthesizer Characteristics
    9. 4.9  DC Characteristics
    10. 4.10 Power-On Reset
    11. 4.11 Thermal Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
    4. 5.4  Configuration Software
    5. 5.5  4-wire Serial Configuration and Data Interface
      1. 5.5.1 Chip Status Byte
      2. 5.5.2 Register Access
      3. 5.5.3 SPI Read
      4. 5.5.4 Command Strobes
      5. 5.5.5 TX FIFO Access
      6. 5.5.6 PATABLE Access
    6. 5.6  Microcontroller Interface and Pin Configuration
      1. 5.6.1 Configuration Interface
      2. 5.6.2 General Control and Status Pins
    7. 5.7  Data Rate Programming
    8. 5.8  Packet Handling Hardware Support
      1. 5.8.1 Packet Format
        1. 5.8.1.1 Packet Length > 255
      2. 5.8.2 Packet Handling
      3. 5.8.3 Packet Handling in Firmware
    9. 5.9  Modulation Formats
      1. 5.9.1 Frequency Shift Keying
      2. 5.9.2 Amplitude Modulation
    10. 5.10 Radio Control
      1. 5.10.1 Power-On Start-Up Sequence
        1. 5.10.1.1 Automatic POR
        2. 5.10.1.2 Manual Reset
      2. 5.10.2 Crystal Control
      3. 5.10.3 Voltage Regulator Control
      4. 5.10.4 Transmit Mode (TX)
      5. 5.10.5 Timing
        1. 5.10.5.1 Overall State Transition Times
        2. 5.10.5.2 Frequency Synthesizer Calibration Time
    11. 5.11 TX FIFO
    12. 5.12 Frequency Programming
    13. 5.13 VCO
      1. 5.13.1 VCO and PLL Self-Calibration
    14. 5.14 Voltage Regulators
    15. 5.15 Output Power Programming
    16. 5.16 General Purpose and Test Output Control Pins
    17. 5.17 Asynchronous and Synchronous Serial Operation
      1. 5.17.1 Asynchronous Serial Operation
      2. 5.17.2 Synchronous Serial Operation
    18. 5.18 System Considerations and Guidelines
      1. 5.18.1 SRD Regulations
      2. 5.18.2 Calibration in Multi-Channel Systems
      3. 5.18.3 Wideband Modulation when not Using Spread Spectrum
      4. 5.18.4 Data Burst Transmissions
      5. 5.18.5 Continuous Transmissions
      6. 5.18.6 Increasing Output Power
    19. 5.19 Configuration Registers
      1. 5.19.1 Configuration Register Details - Registers with preserved values in SLEEP state
      2. 5.19.2 Configuration Register Details - Registers that Lose Programming in SLEEP State
      3. 5.19.3 Status Register Details
    20. 5.20 Development Kit Ordering Information
  6. 6Applications, Implementation, and Layout
    1. 6.1 Bias Resistor
    2. 6.2 Balun and RF Matching
    3. 6.3 Crystal
    4. 6.4 Reference Signal
    5. 6.5 Additional Filtering
    6. 6.6 Power Supply Decoupling
    7. 6.7 PCB Layout Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation from Texas Instruments
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
    7. 7.7 Additional Acronyms
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Specifications

4.1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.
Parameter Min Max Unit Condition
Supply voltage –0.3 3.9 V All supply pins must have the same voltage
Voltage on any digital pin –0.3 VDD + 0.3, max 3.9 V
Voltage on the pins RF_P, RF_N, DCOUPL, RBIAS –0.3 2.0 V
Voltage ramp-up rate 120 kV/µs
Input RF level +10 dBm

4.2 Handling Ratings

Parameter MIN MAX UNIT
Storage temperature range, Tstg (default) –50 150 °C
ESD Stress Voltage, VESD Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) 750 V
Charged Device Model (CDM), per JJESD22-C101(2) 400 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

Parameter Min Max Unit Condition
Operating temperature –40 85 °C
Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

4.4 General Characteristics

Parameter Min Typ Max Unit Condition
Frequency range 300 348 MHz
387 464 MHz If using a 27 MHz crystal, the lower frequency limit for this band is 392 MHz
779 928 MHz
Data rate 0.6 500 kBaud 2-FSK
0.6 250 kBaud GFSK and OOK
0.6 300 kBaud 4-FSK (the data rate in kbps will be twice the baud rate)
Optional Manchester encoding (the data rate in kbps will be half the baud rate)

4.5 Current Consumption

TA = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using SWRR046 and SWRR045.

Parameter Min Typ Max Unit Condition
Current consumption in power down modes 0.2 1 µA Voltage regulator to digital part off, register values retained (SLEEP state). All GDO pins programmed to 0x2F (HW to 0)
100 µA Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)
165 µA Voltage regulator to digital part on, all other modules in power down (XOFF state)
Current consumption 1.7 mA Only voltage regulator to digital part and crystal oscillator running (IDLE state)
8.4 mA Only the frequency synthesizer is running (FSTXON state). This current consumption is also representative for the other intermediate states when going from IDLE to TX, including the calibration state
Current consumption, 315 MHz 27.4 mA Transmit mode, +10 dBm output power
15.0 mA Transmit mode, 0 dBm output power
12.3 mA Transmit mode, –6 dBm output power
Current consumption, 433 MHz 29.2 mA Transmit mode, +10 dBm output power
16.0 mA Transmit mode, 0 dBm output power
13.1 mA Transmit mode, –6 dBm output power
Current consumption, 868/915 MHz 34.2 mA Transmit mode, +12 dBm output power, 868 MHz
30.0 mA Transmit mode, +10 dBm output power, 868 MHz
16.8 mA Transmit mode, 0 dBm output power, 868 MHz
16.4 mA Transmit mode, –6 dBm output power, 868 MHz.
33.4 mA Transmit mode, +11 dBm output power, 915 MHz
30.7 mA Transmit mode, +10 dBm output power, 915 MHz
17.2 mA Transmit mode, 0 dBm output power, 915 MHz
17.0 mA Transmit mode, –6 dBm output power, 915 MHz

4.5.1 Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz

Supply Voltage Supply Voltage Supply Voltage
VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] −40 25 85 −40 25 85 −40 25 85
Current [mA], PATABLE=0xC0, +12 dBm 32.7 31.5 30.5 35.3 34.2 33.3 35.5 34.4 33.5
Current [mA], PATABLE=0xC5, +10 dBm 30.1 29.2 28.3 30.9 30.0 29.4 31.1 30.3 29.6
Current [mA], PATABLE=0x50, 0 dBm 16.4 16.0 15.6 17.3 16.8 16.4 17.6 17.1 16.7

4.5.2 Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz

Supply Voltage Supply Voltage Supply Voltage
VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] −40 25 85 −40 25 85 −40 25 85
Current [mA], PATABLE=0xC0, +11 dBm 31.9 30.7 29.8 34.6 33.4 32.5 34.8 33.6 32.7
Current [mA], PATABLE=0xC3, +10 dBm 30.9 29.8 28.9 31.7 30.7 30.0 31.9 31.0 30.2
Current [mA], PATABLE=0x8E, 0 dBm 17.2 16.8 16.4 17.6 17.2 16.9 17.8 17.4 17.1

4.6 RF Transmit Section

TA = 25°C, VDD = 3.0 V, +10 dBm if nothing else stated. All measurement results are obtained using SWRR046 and SWRR045.
Parameter Min Typ Max Unit Condition
Differential load impedance Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna.
315 MHz 122 + j31 Ω
433 MHz 116 + j41 Ω
868/915 MHz 86.5 + j43 Ω
Output power, highest setting Output power is programmable, and full range is available in all frequency bands. Output power may be restricted by regulatory limits.
See Design Note DN013 SWRA168, which gives the output power and harmonics when using multi-layer inductors. The output power is then typically +10 dBm when operating at 868/915 MHz.
Delivered to a 50-Ω single-ended load through the RF matching network in SWRR046 and SWRR045
315 MHz +10 dBm
433 MHz +10 dBm
868 MHz +12 dBm
915 MHz +11 dBm
Output power, lowest setting −30 dBm Output power is programmable, and full range is available in all frequency bands
Delivered to a 50-Ω single-ended load through the RF matching network in SWRR046 and SWRR045
Harmonics, radiated Measured on SWRR046 and SWRR045 with CW, maximum output power
The antennas used during the radiated measurements (SMAFF-433 from R.W. Badland and Nearson S331 868/915) play a part in attenuating the harmonics
Note: All harmonics are below −41.2 dBm when operating in the 902 - 928 MHz band
2nd Harm, 433 MHz −49 dBm
3rd Harm, 433 MHz −40 dBm
2nd Harm, 868 MHz −47 dBm
3rd Harm, 868 MHz −55 dBm
2nd Harm, 915 MHz −50 dBm
3rd Harm, 915 MHz −54 dBm
Harmonics, conducted Measured with +10 dBm CW at 315 MHz and 433 MHz
315 MHz < −35 dBm Frequencies below 960 MHz
< −53 dBm Frequencies above 960 MHz
433 MHz −43 dBm Frequencies below 1 GHz
< −45 dBm Frequencies above 1 GHz
868 MHz 2nd Harm other harmonics −36 dBm Measured with +12 dBm CW at 868 MHz
< −46 dBm
915 MHz 2nd Harm other harmonics −34 dBm Measured with +11 dBm CW at 915 MHz (requirement is −20 dBc under FCC 15.247)
Other harmonics < −50 dBm
Spurious emissions conducted, harmonics not included Measured with +10 dBm CW at 315 MHz and 433 MHz
315 MHz < −58 Frequencies below 960 MHz
< −53 Frequencies above 960 MHz
433 MHz < −50 Frequencies below 1 GHz
< −54 Frequencies above 1 GHz
< −56 Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz
Measured with +12 dBm CW at 868 MHz
868 MHz < −50 Frequencies below 1 GHz
< −52 Frequencies above 1 GHz
< −53 Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz
All radiated spurious emissions are within the limits of ETSI. The peak conducted spurious emission is −53 dBm at 699 MHz (868 MHz - 169 MHz), which is in a frequency band limited to −54 dBm by EN 300 220 V2.3.1. An alternative filter can be used to reduce the emission at 699 MHz below −54 dBm, for conducted measurements, and is shown in Figure 6-2. See more information in DN017 SWRA168.
For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.
Measured with +11 dBm CW at 915 MHz
915 MHz < −51 Frequencies below 960 MHz
< −54 Frequencies above 960 MHz
TX latency 8 bit Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports.

4.6.1 Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz

Supply Voltage Supply Voltage Supply Voltage
VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] −40 25 85 −40 25 85 −40 25 85
Output Power [dBm], PATABLE=0xC0, +12 dBm 12 11 10 12 12 11 12 12 11
Output Power [dBm], PATABLE=0xC5, +10 dBm 11 10 9 11 10 10 11 10 10
Output Power [dBm], PATABLE=0x50, 0 dBm 1 0 -1 2 1 0 2 1 0

4.6.2 Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz

Supply Voltage Supply Voltage Supply Voltage
VDD = 1.8 V VDD = 3.0 V VDD = 3.6 V
Temperature [°C] −40 25 85 −40 25 85 −40 25 85
Output Power [dBm], PATABLE=0xC0, +11 dBm 11 10 10 12 11 11 12 11 11
Output Power [dBm], PATABLE=0x8E, +0 dBm 2 1 0 2 1 0 2 1 0

4.7 Crystal Oscillator

TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using SWRR046 and SWRR045.
Parameter Min Typ Max Unit Condition
Crystal frequency 26 26 27 MHz For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.
Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.
Load capacitance 10 13 20 pF Simulated over operating conditions
ESR 100 Ω
Start-up time 150 µs This parameter is to a large degree crystal dependent. Measured on SWRR046 and SWRR045 using crystal AT-41CD2 from NDK

4.8 Frequency Synthesizer Characteristics

TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using SWRR046 and SWRR045. Minimum figures are given using a 27 MHz crystal. Typical and maximum figures are given using a 26 MHz crystal.
Parameter Min Typ Max Unit Condition
Programmed frequency resolution 397 FXOSC/216 412 Hz 26- to 27-MHz crystal. The resolution (in Hz) is equal for all frequency bands
Synthesizer frequency tolerance ±40 ppm Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing
RF carrier phase noise –92 dBc/Hz at 50 kHz offset from carrier
RF carrier phase noise –92 dBc/Hz at 100 kHz offset from carrier
RF carrier phase noise –92 dBc/Hz at 200 kHz offset from carrier
RF carrier phase noise –98 dBc/Hz at 500 kHz offset from carrier
RF carrier phase noise –107 dBc/Hz at 1 MHz offset from carrier
RF carrier phase noise –113 dBc/Hz at 2 MHz offset from carrier
RF carrier phase noise –119 dBc/Hz at 5 MHz offset from carrier
RF carrier phase noise –129 dBc/Hz at 10 MHz offset from carrier
PLL turn-on or hop time
(See Table 5-5)		 72 75 75 µs Time from leaving the IDLE state until arriving in the FSTXON or TX state, when not performing calibration. Crystal oscillator running.
PLL calibration time
(See Table 5-6)		 685 712 724 µs Calibration can be initiated manually or automatically before entering or after leaving TX

4.9 DC Characteristics

TA = 25°C if nothing else stated.
Digital Inputs/Outputs Min Max Unit Condition
Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD – 0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD – 0.3 VDD V For up to 4 mA output current
Logic "0" input current N/A –50 nA Input equals 0 V
Logic "1" input current N/A 50 nA Input equals VDD

4.10 Power-On Reset

For proper Power-On-Reset functionality the power supply should comply with the requirements in Section 4.10. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 5.10.1, Power-On Start-Up Sequence, for further details.
Parameter Min Typ Max Unit Condition
Power-up ramp-up time 5 ms From 0 V until reaching 1.8 V
Power off time 1 ms Minimum time between power-on and power-off

4.11 Thermal Characteristics

NAME DESCRIPTION QFN (°C/W)
RθJA Junction-to-ambient thermal resistance 47
RθJC(top) Junction-to-case (top) thermal resistance 45
RθJB Junction-to-board thermal resistance 13.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.12