SWRS105B May   2011  – June 2014 CC115L

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  General Characteristics
    5. 4.5  Current Consumption
      1. 4.5.1 Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz
      2. 4.5.2 Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz
    6. 4.6  RF Transmit Section
      1. 4.6.1 Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz
      2. 4.6.2 Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz
    7. 4.7  Crystal Oscillator
    8. 4.8  Frequency Synthesizer Characteristics
    9. 4.9  DC Characteristics
    10. 4.10 Power-On Reset
    11. 4.11 Thermal Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
    4. 5.4  Configuration Software
    5. 5.5  4-wire Serial Configuration and Data Interface
      1. 5.5.1 Chip Status Byte
      2. 5.5.2 Register Access
      3. 5.5.3 SPI Read
      4. 5.5.4 Command Strobes
      5. 5.5.5 TX FIFO Access
      6. 5.5.6 PATABLE Access
    6. 5.6  Microcontroller Interface and Pin Configuration
      1. 5.6.1 Configuration Interface
      2. 5.6.2 General Control and Status Pins
    7. 5.7  Data Rate Programming
    8. 5.8  Packet Handling Hardware Support
      1. 5.8.1 Packet Format
        1. 5.8.1.1 Packet Length > 255
      2. 5.8.2 Packet Handling
      3. 5.8.3 Packet Handling in Firmware
    9. 5.9  Modulation Formats
      1. 5.9.1 Frequency Shift Keying
      2. 5.9.2 Amplitude Modulation
    10. 5.10 Radio Control
      1. 5.10.1 Power-On Start-Up Sequence
        1. 5.10.1.1 Automatic POR
        2. 5.10.1.2 Manual Reset
      2. 5.10.2 Crystal Control
      3. 5.10.3 Voltage Regulator Control
      4. 5.10.4 Transmit Mode (TX)
      5. 5.10.5 Timing
        1. 5.10.5.1 Overall State Transition Times
        2. 5.10.5.2 Frequency Synthesizer Calibration Time
    11. 5.11 TX FIFO
    12. 5.12 Frequency Programming
    13. 5.13 VCO
      1. 5.13.1 VCO and PLL Self-Calibration
    14. 5.14 Voltage Regulators
    15. 5.15 Output Power Programming
    16. 5.16 General Purpose and Test Output Control Pins
    17. 5.17 Asynchronous and Synchronous Serial Operation
      1. 5.17.1 Asynchronous Serial Operation
      2. 5.17.2 Synchronous Serial Operation
    18. 5.18 System Considerations and Guidelines
      1. 5.18.1 SRD Regulations
      2. 5.18.2 Calibration in Multi-Channel Systems
      3. 5.18.3 Wideband Modulation when not Using Spread Spectrum
      4. 5.18.4 Data Burst Transmissions
      5. 5.18.5 Continuous Transmissions
      6. 5.18.6 Increasing Output Power
    19. 5.19 Configuration Registers
      1. 5.19.1 Configuration Register Details - Registers with preserved values in SLEEP state
      2. 5.19.2 Configuration Register Details - Registers that Lose Programming in SLEEP State
      3. 5.19.3 Status Register Details
    20. 5.20 Development Kit Ordering Information
  6. 6Applications, Implementation, and Layout
    1. 6.1 Bias Resistor
    2. 6.2 Balun and RF Matching
    3. 6.3 Crystal
    4. 6.4 Reference Signal
    5. 6.5 Additional Filtering
    6. 6.6 Power Supply Decoupling
    7. 6.7 PCB Layout Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation from Texas Instruments
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
    7. 7.7 Additional Acronyms
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Terminal Configuration and Functions

3.1 Pin Diagram

The CC115L pinout is shown in Figure 3-1 and Table 3-1. See Section 5.16 for details on the I/O configuration.

po_top_view_swrs105.gifFigure 3-1 Pinout Top View

NOTE

The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.

3.2 Signal Descriptions

Table 3-1 Signal Descriptions

Pin No. Pin Name Pin Type Description
1 SCLK Digital Input Serial configuration interface, clock input
2 SO (GDO1) Digital Output Serial configuration interface, data output
Optional general output pin when CSn is high
3 GDO2 Digital Output Digital output pin for general use:
  • Test signals
  • TX FIFO status signals
  • Clock output, down-divided from XOSC
4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/Os and for the digital core voltage regulator
5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling

NOTE: This pin is intended for use with the CC115L only. It can not be used to provide supply voltage to other devices
6 GDO0 Digital I/O Digital output pin for general use:
  • Test signals
  • TX FIFO status signals
  • Clock output, down-divided from XOSC
  • Serial input TX data
7 CSn Digital Input Serial configuration interface, chip select
8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input
9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
10 XOSC_Q2 Analog I/O Crystal oscillator pin 2
11 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
12 RF_P RF I/O Positive RF output signal from PA in transmit mode
13 RF_N RF I/O Negative RF output signal from PA in transmit mode
14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection
16 GND Ground (Analog) Analog ground connection
17 RBIAS Analog I/O External bias resistor for reference current
18 DGUARD Power (Digital) Power supply connection for digital noise isolation
19 GND Ground (Digital) Ground connection for digital noise isolation
20 SI Digital Input Serial configuration interface, data input