The CC1200 device is a fully integrated single-chip radio transceiver designed for high performance at very low-power and low-voltage operation in cost-effective wireless systems. All filters are integrated, thus removing the need for costly external SAW and IF filters. The device is mainly intended for the ISM (Industrial, Scientific, and Medical) and SRD (Short Range Device) frequency bands at 164–190 MHz, 410–475 MHz, and 820–950 MHz.
The CC1200 device provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and Wake-On-Radio. The main operating parameters of the CC1200 device can be controlled through an SPI interface. In a typical system, the CC1200 device will be used with a microcontroller and only a few external passive components.
The CC1200 and the CC1120 devices are both part of the high-performance transceiver family. The CC1120 device is more optimized toward narrowband applications, while the CC1200 device is optimized toward wideband applications but can also effectively cover narrowband down to 12.5-kHz channels.
Figure 1-1 shows the system block diagram of the CC120x family of devices.
This data manual revision history highlights the changes made to the SWRS123C device-specific data manual to make it an SWRS123D revision.
Changes from C Revision (June 2014) to D Revision
Figure 3-1 shows pin names and locations for the CC1200 device.
The following table lists the pin-out configuration for the CC1200 device.
PIN NO. | PIN NAME | TYPE / DIRECTION | DESCRIPTION |
---|---|---|---|
1 | VDD_GUARD | Power | 2.0–3.6 V VDD |
2 | RESET_N | Digital input | Asynchronous, active-low digital reset |
3 | GPIO3 | Digital I/O | General-purpose I/O |
4 | GPIO2 | Digital I/O | General-purpose I/O |
5 | DVDD | Power | 2.0–3.6 VDD to internal digital regulator |
6 | DCPL | Power | Digital regulator output to external decoupling capacitor |
7 | SI | Digital input | Serial data in |
8 | SCLK | Digital input | Serial data clock |
9 | SO(GPIO1) | Digital I/O | Serial data out (general-purpose I/O) |
10 | GPIO0 | Digital I/O | General-purpose I/O |
11 | CSn | Digital input | Active-low chip select |
12 | DVDD | Power | 2.0–3.6 V VDD |
13 | AVDD_IF | Power | 2.0–3.6 V VDD |
14 | RBIAS | Analog | External high-precision resistor |
15 | AVDD_RF | Power | 2.0–3.6 V VDD |
16 | N.C. | Not connected | |
17 | PA | Analog | Single-ended TX output (requires DC path to VDD) |
18 | TRX_SW | Analog | TX and RX switch. Connected internally to GND in TX and floating (high-impedance) in RX. |
19 | LNA_P | Analog | Differential RX input (requires DC path to ground) |
20 | LNA_N | Analog | Differential RX input (requires DC path to ground) |
21 | DCPL_VCO | Power | Pin for external decoupling of VCO supply regulator |
22 | AVDD_SYNTH1 | Power | 2.0–3.6 V VDD |
23 | LPF0 | Analog | External loop filter components |
24 | LPF1 | Analog | External loop filter components |
25 | AVDD_PFD_CHP | Power | 2.0–3.6 V VDD |
26 | DCPL_PFD_CHP | Power | Pin for external decoupling of PFD and CHP regulator |
27 | AVDD_SYNTH2 | Power | 2.0–3.6 V VDD |
28 | AVDD_XOSC | Power | 2.0–3.6 V VDD |
29 | DCPL_XOSC | Power | Pin for external decoupling of XOSC supply regulator |
30 | XOSC_Q1 | Analog | Crystal oscillator pin 1 (must be grounded if a TCXO or other external clock connected to EXT_XOSC is used) |
31 | XOSC_Q2 | Analog | Crystal oscillator pin 2 (must be left floating if a TCXO or other external clock connected to EXT_XOSC is used) |
32 | EXT_XOSC | Digital input | Pin for external clock input (must be grounded if a regular crystal connected to XOSC_Q1 and XOSC_Q2 is used) |
– | GND | Ground pad | The ground pad must be connected to a solid ground plane. |