JAJSFV9D September   2015  – July 2018 CC1310

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram – RSM Package
    2. 4.2 Signal Descriptions – RSM Package
    3. 4.3 Pin Diagram – RHB Package
    4. 4.4 Signal Descriptions – RHB Package
    5. 4.5 Pin Diagram – RGZ Package
    6. 4.6 Signal Descriptions – RGZ Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  RF Characteristics
    6. 5.6  Receive (RX) Parameters, 861 MHz to 1054 MHz
    7. 5.7  Receive (RX) Parameters, 431 MHz to 527 MHz
    8. 5.8  Transmit (TX) Parameters, 861 MHz to 1054 MHz
    9. 5.9  Transmit (TX) Parameters, 431 MHz to 527 MHz
    10. 5.10 PLL Parameters
    11. 5.11 ADC Characteristics
    12. 5.12 Temperature Sensor
    13. 5.13 Battery Monitor
    14. 5.14 Continuous Time Comparator
    15. 5.15 Low-Power Clocked Comparator
    16. 5.16 Programmable Current Source
    17. 5.17 DC Characteristics
    18. 5.18 Thermal Characteristics
    19. 5.19 Timing and Switching Characteristics
      1. 5.19.1 Reset Timing
        1. Table 5-1 Reset Timing
      2. 5.19.2 Wakeup Timing
        1. Table 5-2 Wakeup Timing
      3. 5.19.3 Clock Specifications
        1. Table 5-3 24-MHz Crystal Oscillator (XOSC_HF)
        2. Table 5-4 32.768-kHz Crystal Oscillator (XOSC_LF)
        3. Table 5-5 48-MHz RC Oscillator (RCOSC_HF)
        4. Table 5-6 32-kHz RC Oscillator (RCOSC_LF)
      4. 5.19.4 Flash Memory Characteristics
        1. Table 5-7 Flash Memory Characteristics
      5. 5.19.5 Synchronous Serial Interface (SSI) Characteristics
        1. Table 5-8 Synchronous Serial Interface (SSI) Characteristics
    20. 5.20 Typical Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Main CPU
    3. 6.3  RF Core
    4. 6.4  Sensor Controller
    5. 6.5  Memory
    6. 6.6  Debug
    7. 6.7  Power Management
    8. 6.8  Clock Systems
    9. 6.9  General Peripherals and Modules
    10. 6.10 Voltage Supply Domains
    11. 6.11 System Architecture
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  デバイスの項目表記
    2. 8.2  ツールとソフトウェア
    3. 8.3  ドキュメントのサポート
    4. 8.4  テキサス・インスツルメンツのローパワーRF Webサイト
    5. 8.5  追加情報
    6. 8.6  コミュニティ・リソース
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Power Management

To minimize power consumption, the CC1310 device supports a number of power modes and power-management features (see Table 6-2).

Table 6-2 Power Modes

MODE SOFTWARE-CONFIGURABLE POWER MODES RESET PIN HELD
ACTIVE IDLE STANDBY SHUTDOWN
CPU Active Off Off Off Off
Flash On Available Off Off Off
SRAM On On On Off Off
Radio Available Available Off Off Off
Supply System On On Duty Cycled Off Off
Current 1.2 mA + 25.5 µA/MHz 570 µA 0.6 µA 185 nA 0.1 µA
Wake-up Time to CPU Active(1) – 14 µs 174 µs 1015 µs 1015 µs
Register Retention Full Full Partial No No
SRAM Retention Full Full Full No No
High-Speed Clock XOSC_HF or
RCOSC_HF		 XOSC_HF or
RCOSC_HF		 Off Off Off
Low-Speed Clock XOSC_LF or
RCOSC_LF		 XOSC_LF or
RCOSC_LF		 XOSC_LF or RCOSC_LF Off Off
Peripherals Available Available Off Off Off
Sensor Controller Available Available Available Off Off
Wake-up on RTC Available Available Available Off Off
Wake-up on Pin Edge Available Available Available Available Off
Wake-up on Reset Pin Available Available Available Available Available
Brown Out Detector (BOD) Active Active Duty Cycled(2) Off N/A
Power On Reset (POR) Active Active Active Active N/A
(1) Not including RTOS overhead.
(2) The Brown Out Detector is disabled between recharge periods in STANDBY. Lowering the supply voltage below the BOD threshold between two recharge periods while in STANDBY may cause the BOD to lock the device upon wakeup until a Reset/POR releases it. To avoid this, it is recommended that STANDBY mode is avoided if there is a risk that the supply voltage (VDDS) may drop below the specified operating voltage range. For the same reason, it is also good practice to ensure that a power cycling operation, such as a battery replacement, triggers a Power-on-reset by ensuring that the VDDS decoupling network is fully depleted before applying supply voltage again (for example, inserting new batteries). This restriction does not apply to CC1310 die revision B or later.

In active mode, the application CM3 CPU is actively executing code. Active mode provides normal operation of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see Table 6-2).

In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked and no code is executed. Any interrupt event returns the processor to active mode.

In standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor Controller event is required to return the device to active mode. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode.

In shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or POR by reading the reset status register. The only state retained in this mode is the latched I/O state and the flash memory contents.

The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller independent of the main CPU. This means that the main CPU does not have to wake up, for example to execute an ADC sample or poll a digital sensor over SPI, thus saving both current and wake-up time that would otherwise be wasted. The Sensor Controller Studio lets the user configure the Sensor Controller and choose which peripherals are controlled and which conditions wake up the main CPU.