JAJSO72 March 2022 CC1311R3
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.