JAJSQN1A december   2022  – june 2023 CC1314R10

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RGZ Package (Top View)
    2. 7.2 Signal Descriptions – RGZ Package
    3. 7.3 Connections for Unused Pins and Modules – RGZ Package
    4. 7.4 Pin Diagram – RSK Package (Top View)
    5. 7.5 Signal Descriptions – RSK Package
    6. 7.6 Connection of Unused Pins and Module – RSK Package
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  RF Frequency Bands
    10. 8.10 861 MHz to 1054 MHz - Receive (RX)
    11. 8.11 861 MHz to 1054 MHz - Transmit (TX) 
    12. 8.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
    13. 8.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Reset Timing
      2. 8.14.2 Wakeup Timing
      3. 8.14.3 Clock Specifications
        1. 8.14.3.1 48 MHz Clock Input (TCXO)
        2. 8.14.3.2 48 MHz Crystal Oscillator (XOSC_HF)
        3. 8.14.3.3 48 MHz RC Oscillator (RCOSC_HF)
        4. 8.14.3.4 2 MHz RC Oscillator (RCOSC_MF)
        5. 8.14.3.5 32.768 kHz Crystal Oscillator (XOSC_LF)
        6. 8.14.3.6 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.14.4 Serial Peripheral Interface (SPI) Characteristics
        1. 8.14.4.1 SPI Characteristics
        2. 8.14.4.2 SPI Master Mode
        3. 8.14.4.3 SPI Master Mode Timing Diagrams
        4. 8.14.4.4 SPI Slave Mode
        5. 8.14.4.5 SPI Slave Mode Timing Diagrams
      5. 8.14.5 UART
        1. 8.14.5.1 UART Characteristics
    15. 8.15 Peripheral Characteristics
      1. 8.15.1 ADC
        1. 8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 8.15.2 DAC
        1. 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.15.3 Temperature and Battery Monitor
        1. 8.15.3.1 Temperature Sensor
        2. 8.15.3.2 Battery Monitor
      4. 8.15.4 Comparators
        1. 8.15.4.1 Low-Power Clocked Comparator
        2. 8.15.4.2 Continuous Time Comparator
      5. 8.15.5 Current Source
        1. 8.15.5.1 Programmable Current Source
      6. 8.15.6 GPIO
        1. 8.15.6.1 GPIO DC Characteristics
    16. 8.16 Typical Characteristics
      1. 8.16.1 MCU Current
      2. 8.16.2 RX Current
      3. 8.16.3 TX Current
      4. 8.16.4 RX Performance
      5. 8.16.5 TX Performance
      6. 8.16.6 ADC Performance
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Proprietary Radio Formats
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems
    14. 9.14 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  12. 11Device and Documentation Support
    1. 11.1 Tools and Software
      1. 11.1.1 SimpleLink™ Microcontroller Platform
    2. 11.2 Documentation Support
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Signal Descriptions – RSK Package

Table 7-3 Signal Descriptions – RSK Package
PIN I/O TYPE DESCRIPTION
NAME NO.
DCDC_SW 47 — Power Output from internal DC/DC converter(1)
DCOUPL 31 — Power For decoupling of internal 1.27 V regulated digital-supply (2)
DIO_1 6 I/O Digital GPIO
DIO_2 7 I/O Digital GPIO
DIO_3 12 I/O Digital GPIO
DIO_4 13 I/O Digital GPIO
DIO_5 14 I/O Digital GPIO, high-drive capability
DIO_6 15 I/O Digital GPIO, high-drive capability
DIO_7 16 I/O Digital GPIO, high-drive capability
DIO_8 18 I/O Digital GPIO
DIO_9 19 I/O Digital GPIO
DIO_10 20 I/O Digital GPIO
DIO_11 21 I/O Digital GPIO
DIO_12 26 I/O Digital GPIO
DIO_13 27 I/O Digital GPIO
DIO_14 28 I/O Digital GPIO
DIO_15 29 I/O Digital GPIO
DIO_16 34 I/O Digital GPIO, JTAG_TDO, high-drive capability
DIO_17 35 I/O Digital GPIO, JTAG_TDI, high-drive capability
DIO_18 36 I/O Digital GPIO
DIO_19 37 I/O Digital GPIO
DIO_20 38 I/O Digital GPIO
DIO_21 39 I/O Digital GPIO
DIO_22 40 I/O Digital GPIO
DIO_23 50 I/O Digital or Analog GPIO, analog capability
DIO_24 51 I/O Digital or Analog GPIO, analog capability
DIO_25 52 I/O Digital or Analog GPIO, analog capability
DIO_26 53 I/O Digital or Analog GPIO, analog capability
DIO_27 54 I/O Digital or Analog GPIO, analog capability
DIO_28 55 I/O Digital or Analog GPIO, analog capability
DIO_29 56 I/O Digital or Analog GPIO, analog capability
DIO_30 57 I/O Digital GPIO, analog capability
DIO_32 8 I/O Digital GPIO
DIO_33 9 I/O Digital GPIO
DIO_34 10 I/O Digital GPIO
DIO_35 11 I/O Digital GPIO
DIO_36 22 I/O Digital GPIO
DIO_37 23 I/O Digital GPIO
DIO_38 24 I/O Digital GPIO
DIO_39 25 I/O Digital GPIO
DIO_40 41 I/O Digital GPIO
DIO_41 42 I/O Digital GPIO
DIO_42 43 I/O Digital GPIO
DIO_43 44 I/O Digital GPIO
DIO_44 45 I/O Digital GPIO
DIO_45 46 I/O Digital GPIO
DIO_46 58 I/O Digital GPIO
DIO_47 59 I/O Digital GPIO
EGP — — GND Ground – exposed ground pad(3)
JTAG_TMSC 32 I/O Digital JTAG TMSC, high-drive capability
JTAG_TCKC 33 I Digital JTAG TCKC
RESET_N 49 I Digital Reset, active low. No internal pullup resistor
RF_P_SUB_1GHZ 1 — RF Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_N_SUB_1GHZ 2 — RF Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RX_TX 3 — RF Optional bias pin for the RF LNA
VDDR 61 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2)(4)(6)
VDDR_RF 64 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2)(5)(6)
VDDS 60 — Power 1.8 V to 3.8 V main chip supply(1)
VDDS2 17 — Power 1.8 V to 3.8 V DIO supply(1)
VDDS3 30 — Power 1.8 V to 3.8 V DIO supply(1)
VDDS_DCDC 48 — Power 1.8 V to 3.8 V DC/DC converter supply
X48M_N 62 — Analog 48 MHz crystal oscillator pin N
X48M_P 63 — Analog 48 MHz crystal oscillator pin P
X32K_Q1 4 — Analog 32 kHz crystal oscillator pin 1
X32K_Q2 5 — Analog 32 kHz crystal oscillator pin 2
(1) For more details, see technical reference manual listed in Section 11.2.
(2) Do not supply external circuitry from this pin.
(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is imperative for proper device operation.
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.