JAJSQN1A december   2022  – june 2023 CC1314R10

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RGZ Package (Top View)
    2. 7.2 Signal Descriptions – RGZ Package
    3. 7.3 Connections for Unused Pins and Modules – RGZ Package
    4. 7.4 Pin Diagram – RSK Package (Top View)
    5. 7.5 Signal Descriptions – RSK Package
    6. 7.6 Connection of Unused Pins and Module – RSK Package
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  RF Frequency Bands
    10. 8.10 861 MHz to 1054 MHz - Receive (RX)
    11. 8.11 861 MHz to 1054 MHz - Transmit (TX) 
    12. 8.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
    13. 8.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Reset Timing
      2. 8.14.2 Wakeup Timing
      3. 8.14.3 Clock Specifications
        1. 8.14.3.1 48 MHz Clock Input (TCXO)
        2. 8.14.3.2 48 MHz Crystal Oscillator (XOSC_HF)
        3. 8.14.3.3 48 MHz RC Oscillator (RCOSC_HF)
        4. 8.14.3.4 2 MHz RC Oscillator (RCOSC_MF)
        5. 8.14.3.5 32.768 kHz Crystal Oscillator (XOSC_LF)
        6. 8.14.3.6 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.14.4 Serial Peripheral Interface (SPI) Characteristics
        1. 8.14.4.1 SPI Characteristics
        2. 8.14.4.2 SPI Master Mode
        3. 8.14.4.3 SPI Master Mode Timing Diagrams
        4. 8.14.4.4 SPI Slave Mode
        5. 8.14.4.5 SPI Slave Mode Timing Diagrams
      5. 8.14.5 UART
        1. 8.14.5.1 UART Characteristics
    15. 8.15 Peripheral Characteristics
      1. 8.15.1 ADC
        1. 8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 8.15.2 DAC
        1. 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.15.3 Temperature and Battery Monitor
        1. 8.15.3.1 Temperature Sensor
        2. 8.15.3.2 Battery Monitor
      4. 8.15.4 Comparators
        1. 8.15.4.1 Low-Power Clocked Comparator
        2. 8.15.4.2 Continuous Time Comparator
      5. 8.15.5 Current Source
        1. 8.15.5.1 Programmable Current Source
      6. 8.15.6 GPIO
        1. 8.15.6.1 GPIO DC Characteristics
    16. 8.16 Typical Characteristics
      1. 8.16.1 MCU Current
      2. 8.16.2 RX Current
      3. 8.16.3 TX Current
      4. 8.16.4 RX Performance
      5. 8.16.5 TX Performance
      6. 8.16.6 ADC Performance
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Proprietary Radio Formats
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems
    14. 9.14 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  12. 11Device and Documentation Support
    1. 11.1 Tools and Software
      1. 11.1.1 SimpleLink™ Microcontroller Platform
    2. 11.2 Documentation Support
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.11 861 MHz to 1054 MHz - Transmit (TX) 

When measured on the LP-EM-CC1314R10 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements are performed conducted. (1)
 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General parameters
Max output power, boost mode VDDR = 1.95 V
Minimum supply voltage (VDDS ) for boost mode is 2.1 V
868 MHz and 915 MHz		 14 dBm
Max output power 868 MHz and 915 MHz 12 dBm
Output power programmable range 868 MHz and 915 MHz, 1dB step size. 34 dB
Output power variation over temperature +10 dBm setting
Over recommended temperature operating range		 ±2 dB
Output power variation over temperature Boost mode +14 dBm setting
Over recommended temperature operating range		 ±1.5 dB
Spurious emissions and harmonics
Spurious emissions (excluding harmonics)(3) 30 MHz to 1 GHz +14 dBm setting
ETSI restricted bands		 < -54 dBm
+14 dBm setting
ETSI outside restricted bands		 < -36 dBm
1 GHz to 12.75 GHz
(outside ETSI restricted bands)		 +14 dBm setting
measured in 1 MHz bandwidth (ETSI)		 < -30 dBm
Spurious emissions out-of-band, 915 MHz(3) 30 MHz to 88 MHz
(within FCC restricted bands)		 +14 dBm setting < -56 dBm
88 MHz to 216 MHz
(within FCC restricted bands)		 +14 dBm setting < -52 dBm
216 MHz to 960 MHz
(within FCC restricted bands)		 +14 dBm setting < -50 dBm
960 MHz to 2390 MHz and above 2483.5 MHz (within FCC restricted band) +14 dBm setting <-42 dBm
1 GHz to 12.75 GHz
(outside FCC restricted bands)		 +14 dBm setting < -40 dBm
Spurious emissions out-of-band, 920.6/928 MHz(3) Below 710 MHz
(ARIB T-108)		 +14 dBm setting < -36 dBm
710 MHz to 900 MHz
(ARIB T-108)		 +14 dBm setting < -55 dBm
900 MHz to 915 MHz
(ARIB T-108)		 +14 dBm setting < -55 dBm
930 MHz to 1000 MHz
(ARIB T-108)		 +14 dBm setting < -55 dBm
1000 MHz to 1215 MHz
(ARIB T-108)		 +14 dBm setting < -45 dBm
Above 1215 MHz
(ARIB T-108)		 +14 dBm setting < -30 dBm
Harmonics Second harmonic +14 dBm setting, 868 MHz < -30 dBm
+14 dBm setting, 915 MHz < -30
Third harmonic +14 dBm setting, 868 MHz < -30 dBm
+14 dBm setting, 915 MHz < -42
Fourth harmonic +14 dBm setting, 868 MHz < -30 dBm
+14 dBm setting, 915 MHz < -30
Fifth harmonic +14 dBm setting, 868 MHz < -30 dBm
+14 dBm setting, 915 MHz < -42
(1) Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory compliance. More details can be found in the device errata.
(2) Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.