JAJSQQ5A december 2022 – june 2023 CC1354R10
ADVANCE INFORMATION
PARAMETERS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCLK 1/tsclk |
SPI clock frequency | Master Mode 1.8 < VDDS < 3.8 |
12 | MHz | ||
Slave Mode 2.7 < VDDS < 3.8 |
8 | |||||
Slave Mode VDDS < 2.7 |
7 | |||||
DCSCK | SCK Duty Cycle | 45 | 50 | 55 | % |