JAJSQG9E April   2023  – September 2024 CC2340R2 , CC2340R5

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagrams
      1. 6.1.1 Pin Diagram—RKP Package (Top View)
      2. 6.1.2 Pin Diagram – RGE Package (Top View)
      3. 6.1.3 Pin Diagram—YBG Package (Top View)
    2.     12
    3. 6.2 Signal Descriptions
      1.      14
      2.      15
      3.      16
      4.      17
      5.      18
      6.      19
      7.      20
      8.      21
      9.      22
      10.      23
      11.      24
      12.      25
      13.      26
      14.      27
      15.      28
      16.      29
      17.      30
      18.      31
    4. 6.3 Connections for Unused Pins and Modules
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  DCDC
    5. 7.5  Global LDO (GLDO)
    6. 7.6  Power Supply and Modules
    7. 7.7  Battery Monitor
    8. 7.8  Temperature Sensor
    9. 7.9  Power Consumption - Power Modes
    10. 7.10 Power Consumption - Radio Modes
    11. 7.11 Nonvolatile (Flash) Memory Characteristics
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 RF Frequency Bands
    14. 7.14 Bluetooth Low Energy - Receive (RX)
    15. 7.15 Bluetooth Low Energy - Transmit (TX)
    16. 7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
    17. 7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
    18. 7.18 Proprietary Radio Modes
    19. 7.19 2.4 GHz RX/TX CW
    20. 7.20 Timing and Switching Characteristics
      1. 7.20.1 Reset Timing
      2. 7.20.2 Wakeup Timing
      3. 7.20.3 Clock Specifications
        1. 7.20.3.1 48 MHz Crystal Oscillator (HFXT)
        2. 7.20.3.2 48 MHz RC Oscillator (HFOSC)
        3. 7.20.3.3 32 kHz Crystal Oscillator (LFXT)
        4. 7.20.3.4 32 kHz RC Oscillator (LFOSC)
    21. 7.21 Peripheral Characteristics
      1. 7.21.1 UART
        1. 7.21.1.1 UART Characteristics
      2. 7.21.2 SPI
        1. 7.21.2.1 SPI Characteristics
        2. 7.21.2.2 SPI Controller Mode
        3. 7.21.2.3 SPI Timing Diagrams - Controller Mode
        4. 7.21.2.4 SPI Peripheral Mode
        5. 7.21.2.5 SPI Timing Diagrams - Peripheral Mode
      3. 7.21.3 I2C
        1. 7.21.3.1 I2C
        2. 7.21.3.2 I2C Timing Diagram
      4. 7.21.4 GPIO
        1. 7.21.4.1 GPIO DC Characteristics
      5. 7.21.5 ADC
        1. 7.21.5.1 Analog-to-Digital Converter (ADC) Characteristics
      6. 7.21.6 Comparators
        1. 7.21.6.1 Ultra-Low Power Comparator
    22. 7.22 Typical Characteristics
      1. 7.22.1 MCU Current
      2. 7.22.2 RX Current
      3. 7.22.3 TX Current
      4. 7.22.4 RX Performance
      5. 7.22.5 TX Performance
      6. 7.22.6 ADC Performance
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Bluetooth 5.3 Low Energy
      2. 8.3.2 802.15.4 (Thread and Zigbee)
    4. 8.4  Memory
    5. 8.5  Cryptography
    6. 8.6  Timers
    7. 8.7  Serial Peripherals and I/O
    8. 8.8  Battery and Temperature Monitor
    9. 8.9  µDMA
    10. 8.10 Debug
    11. 8.11 Power Management
    12. 8.12 Clock Systems
    13. 8.13 Network Processor
  10. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
      1. 10.2.1 SimpleLink™ Microcontroller Platform
    3. 10.3 Documentation Support
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.11 Power Management

To minimize power consumption, the CC2340R supports a number of power modes and power management features (see Table 8-3).

Table 8-3 Power Modes
MODESOFTWARE CONFIGURABLE POWER MODES (1)RESET PIN HELD
ACTIVEIDLESTANDBYSHUTDOWN
CPUActiveOffOffOffOff
FlashOnAvailableOffOffOff
SRAMOnOnRetentionOffOff
RadioAvailableAvailableOffOffOff
Supply SystemOnOnDuty CycledOffOff
CPU register retentionFullFullFull (2)NoNo
SRAM retentionFullFullFullOffOff
48 MHz high-speed clock (HFCLK)HFOSC (tracks HFXT)HFOSC (tracks HFXT)OffOffOff
32 kHz low-speed clock (LFCLK)LFXT or LFOSCLFXT or LFOSCLFXT or LFOSCOffOff
PeripheralsAvailableAvailableIOC, BATMON, RTC, LPCOMPOffOff
Wake-up on RTCN/AAvailableAvailableOffOff
Wake-up on pin edgeN/AAvailableAvailableAvailableOff
Wake-up on reset pinOnOnOnOnOn
Brownout detector (BOD)OnOnDuty CycledOffOff
Power-on reset (POR)OnOnOnOnOn
Watchdog timer (WDT)AvailableAvailableAvailableOffOff
(1) “Available” indicates that the specific IP or feature can be enabled by user application in the corresponding device operating modes. “On” indicates that the specific IP or feature is turned on irrespective of the user application configuration of the device in the corresponding device operating mode. “Off” indicates that the specific IP or feature is turned off and not available for the user application in the corresponding device operating mode.
(2) Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode

In the Active mode, both of MCU and AON power domains are powered. Clock gating is used to minimize power consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU.

In Idle mode the CPU is in sleep but selected peripherals and subsystems (such as the radio) can be active. Infrastructure (Flash, ROM, SRAM, bus) clock gating is possible depending on state of the DMA and debug subsystem.

In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or comparator event (LP-COMP) is required to bring the device back to active mode. Pin Reset will also drive the device from Standby to Active. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode.

In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in this mode are the latched I/O state, 3V register bank, and the flash memory contents.

Note:

The power, RF and clock management for the CC2340R device require specific configuration and handling by software for optimized performance. This configuration and handling is implemented in the TI-provided drivers that are part of the CC2340R software development kit (SDK). Therefore, TI highly recommends using this software framework for all application development on the device. The complete SDK with FreeRTOS, device drivers, and examples are offered free of charge in source code.