SWRS178C February   2015  – July 2016 CC2620

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram - RGZ Package
    2. 4.2 Signal Descriptions - RGZ Package
    3. 4.3 Pin Diagram - RSM Package
    4. 4.4 Signal Descriptions - RSM Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  General Characteristics
    6. 5.6  IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) - RX
    7. 5.7  IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) - TX
    8. 5.8  24-MHz Crystal Oscillator (XOSC_HF)
    9. 5.9  32.768-kHz Crystal Oscillator (XOSC_LF)
    10. 5.10 48-MHz RC Oscillator (RCOSC_HF)
    11. 5.11 32-kHz RC Oscillator (RCOSC_LF)
    12. 5.12 ADC Characteristics
    13. 5.13 Temperature Sensor
    14. 5.14 Battery Monitor
    15. 5.15 Continuous Time Comparator
    16. 5.16 Low-Power Clocked Comparator
    17. 5.17 Programmable Current Source
    18. 5.18 Synchronous Serial Interface (SSI)
    19. 5.19 DC Characteristics
    20. 5.20 Thermal Resistance Characteristics
    21. 5.21 Timing Requirements
    22. 5.22 Switching Characteristics
    23. 5.23 Typical Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Main CPU
    4. 6.4  RF Core
    5. 6.5  Sensor Controller
    6. 6.6  Memory
    7. 6.7  Debug
    8. 6.8  Power Management
    9. 6.9  Clock Systems
    10. 6.10 General Peripherals and Modules
    11. 6.11 Voltage Supply Domains
    12. 6.12 System Architecture
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 4 × 4 External Single-ended (4XS) Application Circuit
      1. 7.2.1 Layout
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
    4. 8.4  Texas Instruments Low-Power RF Website
    5. 8.5  Low-Power RF eNewsletter
    6. 8.6  Community Resources
    7. 8.7  Additional Information
    8. 8.8  Trademarks
    9. 8.9  Electrostatic Discharge Caution
    10. 8.10 Export Control Notice
    11. 8.11 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Supply voltage (VDDS, VDDS2, and VDDS3) VDDR supplied by internal DC-DC regulator or internal GLDO. VDDS_DCDC connected to VDDS on PCB. –0.3 4.1 V
Supply voltage (VDDS(3) and VDDR) External regulator mode (VDDS and VDDR pins connected on PCB) –0.3 2.25 V
Voltage on any digital pin(4)(5) –0.3 VDDSx + 0.3, max 4.1 V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P –0.3 VDDR + 0.3, max 2.25 V
Voltage on ADC input (Vin) Voltage scaling enabled –0.3 VDDS V
Voltage scaling disabled, internal reference –0.3 1.49
Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9
Input RF level 5 dBm
Tstg Storage temperature –40 150 °C
(1) All voltage values are with respect to ground, unless otherwise noted.
(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) In external regulator mode, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog-capable DIO.
(5) Each pin is referenced to a specific VDDSx (VDDS, VDDS2 or VDDS3). For a pin-to-VDDS mapping table, see Table 6-3.

5.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge (ESD) performance Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) All pins ±2500 V
Charged device model (CDM), per JESD22-C101(2) RF pins ±750
Non-RF pins ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Ambient temperature range –40 85 °C
Operating supply voltage (VDDS and VDDR), external regulator mode For operation in 1.8-V systems
(VDDS and VDDR pins connected on PCB, internal DC-DC cannot be used)		 1.7 1.95 V
Operating supply voltage VDDS For operation in battery-powered and 3.3-V systems
(internal DC-DC can be used to minimize power consumption)		 1.8 3.8 V
Operating supply voltages VDDS2 and VDDS3 0.7 × VDDS, min 1.8 3.8 V

5.4 Power Consumption Summary

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V with internal DC-DC converter, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Icore Core current consumption Reset. RESET_N pin asserted or VDDS below Power-on-Reset threshold 100 nA
Shutdown. No clocks running, no retention 150
Standby. With RTC, CPU, RAM and (partial) register retention. RCOSC_LF 1 µA
Standby. With RTC, CPU, RAM and (partial) register retention. XOSC_LF 1.2
Standby. With Cache, RTC, CPU, RAM and (partial) register retention. RCOSC_LF 2.5
Standby. With Cache, RTC, CPU, RAM and (partial) register retention. XOSC_LF 2.7
Idle. Supply Systems and RAM powered. 550
Active. Core running CoreMark 1.45 mA +
31 µA/MHz
Radio RX (1) 5.9 mA
Radio RX(2) 6.1
Radio TX, 0-dBm output power(1) 6.1
Radio TX, 5-dBm output power(2) 9.1
Peripheral Current Consumption (Adds to core current Icore for each peripheral unit activated)(3)
Iperi Peripheral power domain Delta current with domain enabled 20 µA
Serial power domain Delta current with domain enabled 13 µA
RF Core Delta current with power domain enabled, clock enabled, RF core idle 237 µA
µDMA Delta current with clock enabled, module idle 130 µA
Timers Delta current with clock enabled, module idle 113 µA
I2C Delta current with clock enabled, module idle 12 µA
I2S Delta current with clock enabled, module idle 36 µA
SSI Delta current with clock enabled, module idle 93 µA
UART Delta current with clock enabled, module idle 164 µA
(1) Single-ended RF mode is optimized for size and power consumption. Measured on CC2650EM-4XS.
(2) Differential RF mode is optimized for RF performance. Measured on CC2650EM-5XD.
(3) Iperi is not supported in Standby or Shutdown.

5.5 General Characteristics

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FLASH MEMORY
Supported flash erase cycles before failure 100 k Cycles
Flash page/sector erase current Average delta current 12.6 mA
Flash page/sector size 4 KB
Flash write current Average delta current, 4 bytes at a time 8.15 mA
Flash page/sector erase time(1) 8 ms
Flash write time(1) 4 bytes at a time 8 µs
(1) This number is dependent on Flash aging and will increase over time and erase cycles.

5.6 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver sensitivity Differential mode. Measured at the CC2650EM-5XD SMA connector, PER = 1% –100 dBm
Receiver sensitivity Single-ended mode. Measured on CC2650EM-4XS, at the SMA connector, PER = 1% –97 dBm
Receiver saturation Measured at the CC2650EM-5XD SMA connector, PER = 1% +4 dBm
Adjacent channel rejection Wanted signal at –82 dBm, modulated interferer at ±5 MHz, PER = 1% 39 dB
Alternate channel rejection Wanted signal at –82 dBm, modulated interferer at ±10 MHz, PER = 1% 52 dB
Channel rejection, ±15 MHz or more Wanted signal at –82 dBm, undesired signal is IEEE 802.15.4 modulated channel, stepped through all channels 2405 to 2480 MHz, PER = 1% 57 dB
Blocking and desensitization,
5 MHz from upper band edge 		Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 64 dB
Blocking and desensitization,
10 MHz from upper band edge		 Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 64 dB
Blocking and desensitization,
20 MHz from upper band edge		 Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 65 dB
Blocking and desensitization,
50 MHz from upper band edge		 Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 68 dB
Blocking and desensitization,
–5 MHz from lower band edge		 Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 63 dB
Blocking and desensitization,
–10 MHz from lower band edge		 Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 63 dB
Blocking and desensitization,
–20 MHz from lower band edge		 Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 65 dB
Blocking and desensitization,
–50 MHz from lower band edge		 Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 67 dB
Spurious emissions, 30 MHz to 1000 MHz Conducted measurement in a 50-Ω single-ended load. Suitable for systems targeting compliance with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66 –71 dBm
Spurious emissions, 1 GHz to 12.75 GHz Conducted measurement in a 50 Ω single-ended load. Suitable for systems targeting compliance with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66 –62 dBm
Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency >200 ppm
Symbol rate error tolerance Difference between incoming symbol rate and the internally generated symbol rate >1000 ppm
RSSI dynamic range 100 dB
RSSI accuracy ±4 dB

5.7 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output power, highest setting Delivered to a single-ended 50-Ω load through a balun 5 dBm
Output power, highest setting Measured on CC2650EM-4XS, delivered to a single-ended 50-Ω load 2 dBm
Output power, lowest setting Delivered to a single-ended 50-Ω load through a balun –21 dBm
Error vector magnitude At maximum output power 2%
Spurious emission conducted measurement f < 1 GHz, outside restricted bands –43 dBm
f < 1 GHz, restricted bands ETSI –65
f < 1 GHz, restricted bands FCC –76
f > 1 GHz, including harmonics –46
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)

5.8 24-MHz Crystal Oscillator (XOSC_HF)

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ESR Equivalent series resistance(2) 6 pF < CL ≤ 9 pF 20 60 Ω
ESR Equivalent series resistance(2) 5 pF < CL ≤ 6 pF 80 Ω
LM Motional inductance(2) Relates to load capacitance
(CL in Farads)		 < 1.6 × 10–24 / CL2 H
CL Crystal load capacitance(2) 5 9 pF
Crystal frequency(2)(3) 24 MHz
Crystal frequency tolerance(2)(4) –40 40 ppm
Start-up time(3)(5) 150 µs
(1) Probing or otherwise stopping the XTAL while the DC-DC converter is enabled may cause permanent damage to the device.
(2) The crystal manufacturer's specification must satisfy this requirement
(3) Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V
(4) Includes initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per IEEE 802.15.4 specification.
(5) Kick-started based on a temperature and aging compensated RCOSC_HF using precharge injection.

5.9 32.768-kHz Crystal Oscillator (XOSC_LF)

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Crystal frequency(1) 32.768 kHz
ESR Equivalent series resistance(1) 30 100 kΩ
CL Crystal load capacitance(1) 6 12 pF
(1) The crystal manufacturer's specification must satisfy this requirement

5.10 48-MHz RC Oscillator (RCOSC_HF)

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency 48 MHz
Uncalibrated frequency accuracy ±1%
Calibrated frequency accuracy(1) ±0.25%
Start-up time 5 µs
(1) Accuracy relative to the calibration source (XOSC_HF).

5.11 32-kHz RC Oscillator (RCOSC_LF)

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Calibrated frequency(1) 32.8 kHz
Temperature coefficient 50 ppm/°C
(1) The frequency accuracy of the Real Time Clock (RTC) is not directly dependent on the frequency accuracy of the 32-kHz RC Oscillator. The RTC can be calibrated to an accuracy within ±500 ppm of 32.768 kHz by measuring the frequency error of RCOSC_LF relative to XOSC_HF and compensating the RTC tick speed. The procedure is explained in Running Bluetooth® Low Energy on CC2640 Without 32 kHz Crystal.

5.12 ADC Characteristics

Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Resolution 12 Bits
Sample rate 200 ksps
Offset Internal 4.3-V equivalent reference(2) 2 LSB
Gain error Internal 4.3-V equivalent reference(2) 2.4 LSB
DNL(4) Differential nonlinearity >–1 LSB
INL(5) Integral nonlinearity ±3 LSB
ENOB Effective number of bits Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 9.8 Bits
VDDS as reference, 200 ksps, 9.6-kHz input tone 10
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		 11.1
THD Total harmonic distortion Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 –65 dB
VDDS as reference, 200 ksps, 9.6-kHz input tone –69
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		 –71
SINAD,
SNDR		 Signal-to-noise
and
Distortion ratio		 Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 60 dB
VDDS as reference, 200 ksps, 9.6-kHz input tone 63
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		 69
SFDR Spurious-free dynamic range Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 67 dB
VDDS as reference, 200 ksps, 9.6-kHz input tone 72
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		 73
Conversion time Serial conversion, time-to-output, 24-MHz clock 50 clock-cycles
Current consumption Internal 4.3-V equivalent reference(2) 0.66 mA
Current consumption VDDS as reference 0.75 mA
Reference voltage Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1. 4.3(2)(3) V
Reference voltage Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3V) as follows: Vref=4.3V*1408/4095 1.48 V
Reference voltage VDDS as reference (Also known as RELATIVE) (input voltage scaling enabled) VDDS V
Reference voltage VDDS as reference (Also known as RELATIVE) (input voltage scaling disabled) VDDS / 2.82(3) V
Input Impedance 200 ksps, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time >1 MΩ
(1) Using IEEE Std 1241™-2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
(3) Applied voltage must be within absolute maximum ratings (Section 5.1) at all times.
(4) No missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see Figure 5-22).
(5) For a typical example, see Figure 5-23.

5.13 Temperature Sensor

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 4 °C
Range –40 85 °C
Accuracy ±5 °C
Supply voltage coefficient(1) 3.2 °C/V
(1) Automatically compensated when using supplied driver libraries.

5.14 Battery Monitor

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 50 mV
Range 1.8 3.8 V
Accuracy 13 mV

5.15 Continuous Time Comparator

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
External reference voltage 0 VDDS V
Internal reference voltage DCOUPL as reference 1.27 V
Offset 3 mV
Hysteresis <2 mV
Decision time Step from –10 mV to 10 mV 0.72 µs
Current consumption when enabled(1) 8.6 µA
(1) Additionally, the bias module must be enabled when running in standby mode.

5.16 Low-Power Clocked Comparator

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Clock frequency 32 kHz
Internal reference voltage, VDDS / 2 1.49 – 1.51 V
Internal reference voltage, VDDS / 3 1.01 – 1.03 V
Internal reference voltage, VDDS / 4 0.78 – 0.79 V
Internal reference voltage, DCOUPL / 1 1.25 – 1.28 V
Internal reference voltage, DCOUPL / 2 0.63 – 0.65 V
Internal reference voltage, DCOUPL / 3 0.42 – 0.44 V
Internal reference voltage, DCOUPL / 4 0.33 – 0.34 V
Offset <2 mV
Hysteresis <5 mV
Decision time Step from –50 mV to 50 mV <1 clock-cycle
Current consumption when enabled 362 nA

5.17 Programmable Current Source

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current source programmable output range 0.25 – 20 µA
Resolution 0.25 µA
Current consumption(1) Including current source at maximum programmable output 23 µA
(1) Additionally, the bias module must be enabled when running in standby mode.

5.18 Synchronous Serial Interface (SSI)

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
S1(1) tclk_per (SSIClk period) Device operating as SLAVE 12 65024 system clocks
S2 (1) tclk_high (SSIClk high time) Device operating as SLAVE 0.5 tclk_per
S3(1) tclk_low (SSIClk low time) Device operating as SLAVE 0.5 tclk_per
S1 (TX only)(1) tclk_per (SSIClk period) One-way communication to SLAVE - Device operating as MASTER 4 65024 system clocks
S1 (TX and RX)(1) tclk_per (SSIClk period) Normal duplex operation - Device operating as MASTER 8 65024 system clocks
S2 (1) tclk_high (SSIClk high time) Device operating as MASTER 0.5 tclk_per
S3 (1) tclk_low(SSIClk low time) Device operating as MASTER 0.5 tclk_per
(1) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
CC2620 td_1_swrs158.gif Figure 5-1 SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
CC2620 td_2_swrs158.gif Figure 5-2 SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
CC2620 td_3_swrs158.gif Figure 5-3 SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

5.19 DC Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25°C, VDDS = 1.8 V
GPIO VOH at 8-mA load IOCURR = 2, high-drive GPIOs only 1.32 1.54 V
GPIO VOL at 8-mA load IOCURR = 2, high-drive GPIOs only 0.26 0.32 V
GPIO VOH at 4-mA load IOCURR = 1 1.32 1.58 V
GPIO VOL at 4-mA load IOCURR = 1 0.21 0.32 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 71.7 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 21.1 µA
GPIO high/low input transition,
no hysteresis		 IH = 0, transition between reading 0 and reading 1 0.88 V
GPIO low-to-high input transition,
with hysteresis		 IH = 1, transition voltage for input read as 0 → 1 1.07 V
GPIO high-to-low input transition,
with hysteresis		 IH = 1, transition voltage for input read as 1 → 0 0.74 V
GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.33 V
TA = 25°C, VDDS = 3.0 V
GPIO VOH at 8-mA load IOCURR = 2, high-drive GPIOs only 2.68 V
GPIO VOL at 8-mA load IOCURR = 2, high-drive GPIOs only 0.33 V
GPIO VOH at 4-mA load IOCURR = 1 2.72 V
GPIO VOL at 4-mA load IOCURR = 1 0.28 V
TA = 25°C, VDDS = 3.8 V
GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 277 µA
GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 113 µA
GPIO high/low input transition,
no hysteresis		 IH = 0, transition between reading 0 and reading 1 1.67 V
GPIO low-to-high input transition,
with hysteresis		 IH = 1, transition voltage for input read as 0 → 1 1.94 V
GPIO high-to-low input transition,
with hysteresis		 IH = 1, transition voltage for input read as 1 → 0 1.54 V
GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.4 V
TA = 25°C
VIH Lowest GPIO input voltage reliably interpreted as a «High» 0.8 VDDS(1)
VIL Highest GPIO input voltage reliably interpreted as a «Low» 0.2 VDDS(1)
(1) Each GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in Section 8.3 for more details.

5.20 Thermal Resistance Characteristics

NAME DESCRIPTION RSM (°C/W)(1)(2) RGZ (°C/W)(1)(2)
RθJA Junction-to-ambient thermal resistance 36.9 29.6
RθJC(top) Junction-to-case (top) thermal resistance 30.3 15.7
RθJB Junction-to-board thermal resistance 7.6 6.2
PsiJT Junction-to-top characterization parameter 0.4 0.3
PsiJB Junction-to-board characterization parameter 7.4 6.2
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 1.9
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air).
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
  • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements.
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.

5.21 Timing Requirements

MIN NOM MAX UNIT
Rising supply-voltage slew rate 0 100 mV/µs
Falling supply-voltage slew rate 0 20 mV/µs
Falling supply-voltage slew rate, with low-power flash settings(1) 3 mV/µs
Positive temperature gradient in standby(3) No limitation for negative temperature gradient, or outside standby mode 5 °C/s
CONTROL INPUT AC CHARACTERISTICS(2)
RESET_N low duration 1 µs
(1) For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see Figure 7-1) must be used to ensure compliance with this slew rate.
(2) TA = –40°C to 85°C, VDDS = 1.7 V to 3.8 V, unless otherwise noted.
(3) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see Section 5.11).

5.22 Switching Characteristics

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
WAKEUP AND TIMING
Idle → Active 14 µs
Standby → Active 151 µs
Shutdown → Active 1015 µs

5.23 Typical Characteristics

CC2620 D002_SWRS176_ZigBee.gif
Figure 5-4 IEEE 802.15.4 Sensitivity vs Temperature
CC2620 D019_SWRS158.gif
Figure 5-6 IEEE 802.15.4 Sensitivity vs Channel Frequency
CC2620 D003_SWRS158.gif
Figure 5-8 TX Output Power vs Supply Voltage (VDDS)
CC2620 D015_SWRS158.gif
Figure 5-10 TX Current Consumption
vs Supply Voltage (VDDS)
CC2620 D001_SWRS158.gif
Figure 5-12 RX Mode Current Consumption vs Temperature
CC2620 D006_SWRS158.gif
Figure 5-14 Active Mode (MCU Running, No Peripherals)
Current Consumption vs Temperature
CC2620 D008_SWRS158.gif
Figure 5-16 Standby Mode Current Consumption With RCOSC RTC vs Temperature
CC2620 D012_SWRS158.gif
Figure 5-18 SoC ADC Output vs Supply Voltage (Fixed Input, Internal Reference, No Scaling)
CC2620 D009A_SWRS158.gif
Figure 5-20 SoC ADC ENOB vs Sampling Frequency
(Input Frequency = FS / 10)
CC2620 D005_SWRS158.gif
Figure 5-5 IEEE 802.15.4 Sensitivity vs Supply Voltage (VDDS)
CC2620 D014_SWRS176.gif
Figure 5-7 TX Output Power vs Temperature
CC2620 D021_SWRS158.gif
Figure 5-9 TX Output Power
vs Channel Frequency
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Figure 5-11 RX Mode Current vs Supply Voltage (VDDS)
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Figure 5-13 TX Mode Current Consumption vs Temperature
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Figure 5-15 Active Mode (MCU Running, No Peripherals) Current Consumption vs Supply Voltage (VDDS)
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Figure 5-17 SoC ADC Effective Number of Bits vs Input Frequency (Internal Reference, No Scaling)
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Figure 5-19 SoC ADC Output vs Temperature (Fixed Input, Internal Reference, No Scaling)
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Figure 5-21 Standby Mode Supply Current vs Temperature
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Figure 5-22 SoC ADC DNL vs ADC Code (Internal Reference, No Scaling)
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Figure 5-23 SoC ADC INL vs ADC Code (Internal Reference, No Scaling)