JAJSCW4C december 2016 – september 2020 CC2640R2F
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NAME | NO. | TYPE | DESCRIPTION |
---|---|---|---|
DCDC_SW | 33 | Power | Output from internal DC/DC(1) |
DCOUPL | 23 | Power | 1.27-V regulated digital-supply decoupling capacitor(2) |
DIO_0 | 5 | Digital I/O | GPIO, Sensor Controller |
DIO_1 | 6 | Digital I/O | GPIO, Sensor Controller |
DIO_2 | 7 | Digital I/O | GPIO, Sensor Controller |
DIO_3 | 8 | Digital I/O | GPIO, Sensor Controller |
DIO_4 | 9 | Digital I/O | GPIO, Sensor Controller |
DIO_5 | 10 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_6 | 11 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_7 | 12 | Digital I/O | GPIO, Sensor Controller, high-drive capability |
DIO_8 | 14 | Digital I/O | GPIO |
DIO_9 | 15 | Digital I/O | GPIO |
DIO_10 | 16 | Digital I/O | GPIO |
DIO_11 | 17 | Digital I/O | GPIO |
DIO_12 | 18 | Digital I/O | GPIO |
DIO_13 | 19 | Digital I/O | GPIO |
DIO_14 | 20 | Digital I/O | GPIO |
DIO_15 | 21 | Digital I/O | GPIO |
DIO_16 | 26 | Digital I/O | GPIO, JTAG_TDO, high-drive capability |
DIO_17 | 27 | Digital I/O | GPIO, JTAG_TDI, high-drive capability |
DIO_18 | 28 | Digital I/O | GPIO |
DIO_19 | 29 | Digital I/O | GPIO |
DIO_20 | 30 | Digital I/O | GPIO |
DIO_21 | 31 | Digital I/O | GPIO |
DIO_22 | 32 | Digital I/O | GPIO |
DIO_23 | 36 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_24 | 37 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_25 | 38 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_26 | 39 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_27 | 40 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_28 | 41 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_29 | 42 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
DIO_30 | 43 | Digital/Analog I/O | GPIO, Sensor Controller, Analog |
JTAG_TMSC | 24 | Digital I/O | JTAG TMSC, high-drive capability |
JTAG_TCKC | 25 | Digital I/O | JTAG TCKC(3) |
RESET_N | 35 | Digital input | Reset, active-low. No internal pullup. |
RF_P | 1 | RF I/O | Positive RF input signal to LNA during RX Positive RF output signal to PA during TX |
RF_N | 2 | RF I/O | Negative RF input signal to LNA during RX Negative RF output signal to PA during TX |
VDDR | 45 | Power | 1.7-V to 1.95-V supply, typically connect to output of internal DC/DC(2)(4) |
VDDR_RF | 48 | Power | 1.7-V to 1.95-V supply, typically connect to output of internal DC/DC(2)(5) |
VDDS | 44 | Power | 1.8-V to 3.8-V main chip supply(1) |
VDDS2 | 13 | Power | 1.8-V to 3.8-V DIO supply(1) |
VDDS3 | 22 | Power | 1.8-V to 3.8-V DIO supply(1) |
VDDS_DCDC | 34 | Power | 1.8-V to 3.8-V DC/DC supply |
X32K_Q1 | 3 | Analog I/O | 32-kHz crystal oscillator pin 1 |
X32K_Q2 | 4 | Analog I/O | 32-kHz crystal oscillator pin 2 |
X24M_N | 46 | Analog I/O | 24-MHz crystal oscillator pin 1 |
X24M_P | 47 | Analog I/O | 24-MHz crystal oscillator pin 2 |
EGP | Power | Ground – Exposed Ground Pad |