The debug subsystem implements two IEEE standards for debug and test purposes:

IEEE 1149.7 Class 4: Reduced-pin and Enhanced-functionality Test Access port and Boundary-scan Architecture. This is known by the acronym cJTAG (compact JTAG) and this device uses only two pins to communicate to the target: TMS (JTAG_TMSC) and TCK (JTAG_TCKC). This is the default mode of operation

IEEE standard 1149.1: Test Access Port and Boundary Scan Architecture Test Access Port (TAP). This standard is known by the acronym JTAG and this device uses four pins to communicate to the target: TMS (JTAG_TMSC), TCK (JTAG_TCKC), TDI (JTAG_TDI) and TDO (JTAG_TDO).

The debug subsystem also implements a user-configurable firewall to control unauthorized access to debug/test ports.

Also featured is EnergyTrace/EnergyTrace++. This technology implements an improved method for measuring MCU current consumption, which features a very high dynamic range (from sub-µA to hundreds of mA), high sample rate (up to 256 kSamples/s) and the ability to track the CPU and peripheral power states.

Two modes of operation can be configured. EnergyTrace measures the overall MCU current consumption and allows maximum accuracy and speed to track ultra low-power states as well as the fast power transitions during radio transmission and reception. EnergyTrace++ tracks the various power states of both the CPU and its Peripherals as well as the system clocks, allowing a close monitoring of the overall device activity.