SWRS158B February   2015  – July 2016 CC2650

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram - RGZ Package
    2. 4.2 Signal Descriptions - RGZ Package
    3. 4.3 Pin Diagram - RHB Package
    4. 4.4 Signal Descriptions - RHB Package
    5. 4.5 Pin Diagram - RSM Package
    6. 4.6 Signal Descriptions - RSM Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  General Characteristics
    6. 5.6  1-Mbps GFSK (Bluetooth low energy Technology) - RX
    7. 5.7  1-Mbps GFSK (Bluetooth low energy Technology) - TX
    8. 5.8  2-Mbps GFSK (Bluetooth 5) - RX
    9. 5.9  2-Mbps GFSK (Bluetooth 5) - TX
    10. 5.10 5-Mbps (Proprietary) - RX
    11. 5.11 5-Mbps (Proprietary) - TX
    12. 5.12 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) - RX
    13. 5.13 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) - TX
    14. 5.14 24-MHz Crystal Oscillator (XOSC_HF)
    15. 5.15 32.768-kHz Crystal Oscillator (XOSC_LF)
    16. 5.16 48-MHz RC Oscillator (RCOSC_HF)
    17. 5.17 32-kHz RC Oscillator (RCOSC_LF)
    18. 5.18 ADC Characteristics
    19. 5.19 Temperature Sensor
    20. 5.20 Battery Monitor
    21. 5.21 Continuous Time Comparator
    22. 5.22 Low-Power Clocked Comparator
    23. 5.23 Programmable Current Source
    24. 5.24 Synchronous Serial Interface (SSI)
    25. 5.25 DC Characteristics
    26. 5.26 Thermal Resistance Characteristics
    27. 5.27 Timing Requirements
    28. 5.28 Switching Characteristics
    29. 5.29 Typical Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Main CPU
    4. 6.4  RF Core
    5. 6.5  Sensor Controller
    6. 6.6  Memory
    7. 6.7  Debug
    8. 6.8  Power Management
    9. 6.9  Clock Systems
    10. 6.10 General Peripherals and Modules
    11. 6.11 Voltage Supply Domains
    12. 6.12 System Architecture
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 5 × 5 External Differential (5XD) Application Circuit
      1. 7.2.1 Layout
    3. 7.3 4 × 4 External Single-ended (4XS) Application Circuit
      1. 7.3.1 Layout
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
    4. 8.4  Texas Instruments Low-Power RF Website
    5. 8.5  Low-Power RF eNewsletter
    6. 8.6  Community Resources
    7. 8.7  Additional Information
    8. 8.8  Trademarks
    9. 8.9  Electrostatic Discharge Caution
    10. 8.10 Export Control Notice
    11. 8.11 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSM|32
  • RHB|32
  • RGZ|48
サーマルパッド・メカニカル・データ
発注情報

4 Terminal Configuration and Functions

4.1 Pin Diagram – RGZ Package

CC2650 PO_CC26xx_QFN32_7x7.gif

NOTE:

I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.
Figure 4-1 RGZ Package
48-Pin VQFN
(7-mm × 7-mm) Pinout, 0.5-mm Pitch

4.2 Signal Descriptions – RGZ Package

Table 4-1 Signal Descriptions – RGZ Package

NAME NO. TYPE DESCRIPTION
DCDC_SW 33 Power Output from internal DC-DC(1)
DCOUPL 23 Power 1.27-V regulated digital-supply decoupling capacitor(2)
DIO_0 5 Digital I/O GPIO, Sensor Controller
DIO_1 6 Digital I/O GPIO, Sensor Controller
DIO_2 7 Digital I/O GPIO, Sensor Controller
DIO_3 8 Digital I/O GPIO, Sensor Controller
DIO_4 9 Digital I/O GPIO, Sensor Controller
DIO_5 10 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_6 11 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_7 12 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_8 14 Digital I/O GPIO
DIO_9 15 Digital I/O GPIO
DIO_10 16 Digital I/O GPIO
DIO_11 17 Digital I/O GPIO
DIO_12 18 Digital I/O GPIO
DIO_13 19 Digital I/O GPIO
DIO_14 20 Digital I/O GPIO
DIO_15 21 Digital I/O GPIO
DIO_16 26 Digital I/O GPIO, JTAG_TDO, high-drive capability
DIO_17 27 Digital I/O GPIO, JTAG_TDI, high-drive capability
DIO_18 28 Digital I/O GPIO
DIO_19 29 Digital I/O GPIO
DIO_20 30 Digital I/O GPIO
DIO_21 31 Digital I/O GPIO
DIO_22 32 Digital I/O GPIO
DIO_23 36 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_24 37 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_25 38 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_26 39 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_27 40 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_28 41 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_29 42 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_30 43 Digital/Analog I/O GPIO, Sensor Controller, Analog
JTAG_TMSC 24 Digital I/O JTAG TMSC, high-drive capability
JTAG_TCKC 25 Digital I/O JTAG TCKC
RESET_N 35 Digital input Reset, active-low. No internal pullup.
RF_P 1 RF I/O Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RF_N 2 RF I/O Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
VDDR 45 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(3)
VDDR_RF 48 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(4)
VDDS 44 Power 1.8-V to 3.8-V main chip supply(1)
VDDS2 13 Power 1.8-V to 3.8-V DIO supply(1)
VDDS3 22 Power 1.8-V to 3.8-V DIO supply(1)
VDDS_DCDC 34 Power 1.8-V to 3.8-V DC-DC supply
X32K_Q1 3 Analog I/O 32-kHz crystal oscillator pin 1
X32K_Q2 4 Analog I/O 32-kHz crystal oscillator pin 2
X24M_N 46 Analog I/O 24-MHz crystal oscillator pin 1
X24M_P 47 Analog I/O 24-MHz crystal oscillator pin 2
EGP Power Ground – Exposed Ground Pad
(1) See technical reference manual (listed in Section 8.3) for more details.
(2) Do not supply external circuitry from this pin.
(3) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.

4.3 Pin Diagram – RHB Package

CC2650 PO_CC26xx_QFN32_5x5.gif

NOTE:

I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.
Figure 4-2 RHB Package
32-Pin VQFN
(5-mm × 5-mm) Pinout, 0.5-mm Pitch

4.4 Signal Descriptions – RHB Package

Table 4-2 Signal Descriptions – RHB Package

NAME NO. TYPE DESCRIPTION
DCDC_SW 17 Power Output from internal DC-DC(1)
DCOUPL 12 Power 1.27-V regulated digital-supply decoupling(2)
DIO_0 6 Digital I/O GPIO, Sensor Controller
DIO_1 7 Digital I/O GPIO, Sensor Controller
DIO_2 8 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_3 9 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_4 10 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_5 15 Digital I/O GPIO, High drive capability, JTAG_TDO
DIO_6 16 Digital I/O GPIO, High drive capability, JTAG_TDI
DIO_7 20 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_8 21 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_9 22 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_10 23 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_11 24 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_12 25 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_13 26 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_14 27 Digital/Analog I/O GPIO, Sensor Controller, Analog
JTAG_TMSC 13 Digital I/O JTAG TMSC, high-drive capability
JTAG_TCKC 14 Digital I/O JTAG TCKC
RESET_N 19 Digital input Reset, active-low. No internal pullup.
RF_N 2 RF I/O Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_P 1 RF I/O Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RX_TX 3 RF I/O Optional bias pin for the RF LNA
VDDR 29 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(3)(2)
VDDR_RF 32 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(4)
VDDS 28 Power 1.8-V to 3.8-V main chip supply(1)
VDDS2 11 Power 1.8-V to 3.8-V GPIO supply(1)
VDDS_DCDC 18 Power 1.8-V to 3.8-V DC-DC supply
X32K_Q1 4 Analog I/O 32-kHz crystal oscillator pin 1
X32K_Q2 5 Analog I/O 32-kHz crystal oscillator pin 2
X24M_N 30 Analog I/O 24-MHz crystal oscillator pin 1
X24M_P 31 Analog I/O 24-MHz crystal oscillator pin 2
EGP Power Ground – Exposed Ground Pad
(1) See technical reference manual (listed in Section 8.3) for more details.
(2) Do not supply external circuitry from this pin.
(3) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.

4.5 Pin Diagram – RSM Package

CC2650 PO_CC26xx_QFN32_DCDC.gif

NOTE:

I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.
Figure 4-3 RSM Package
32-Pin VQFN
(4-mm × 4-mm) Pinout, 0.4-mm Pitch

4.6 Signal Descriptions – RSM Package

Table 4-3 Signal Descriptions – RSM Package

NAME NO. TYPE DESCRIPTION
DCDC_SW 18 Power Output from internal DC-DC. (1). Tie to ground for external regulator mode (1.7-V to 1.95-V operation)
DCOUPL 12 Power 1.27-V regulated digital-supply decoupling capacitor(2)
DIO_0 8 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_1 9 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_2 10 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_3 15 Digital I/O GPIO, High drive capability, JTAG_TDO
DIO_4 16 Digital I/O GPIO, High drive capability, JTAG_TDI
DIO_5 22 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_6 23 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_7 24 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_8 25 Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_9 26 Digital/Analog I/O GPIO, Sensor Controller, Analog
JTAG_TMSC 13 Digital I/O JTAG TMSC
JTAG_TCKC 14 Digital I/O JTAG TCKC
RESET_N 21 Digital Input Reset, active-low. No internal pullup.
RF_N 2 RF I/O Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_P 1 RF I/O Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RX_TX 4 RF I/O Optional bias pin for the RF LNA
VDDR 28 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC. (2)(3)
VDDR_RF 32 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(4)
VDDS 27 Power 1.8-V to 3.8-V main chip supply(1)
VDDS2 11 Power 1.8-V to 3.8-V GPIO supply(1)
VDDS_DCDC 19 Power 1.8-V to 3.8-V DC-DC supply. Tie to ground for external regulator mode (1.7-V to 1.95-V operation).
VSS 3, 7, 17, 20, 29 Power Ground
X32K_Q1 5 Analog I/O 32-kHz crystal oscillator pin 1
X32K_Q2 6 Analog I/O 32-kHz crystal oscillator pin 2
X24M_N 30 Analog I/O 24-MHz crystal oscillator pin 1
X24M_P 31 Analog I/O 24-MHz crystal oscillator pin 2
EGP Power Ground – Exposed Ground Pad
(1) See technical reference manual (listed in Section 8.3) for more details.
(2) Do not supply external circuitry from this pin.
(3) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.