JAJSI59C October 2019 – April 2024 CC2652P
PRODUCTION DATA
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PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Input voltage range | 0 | VDDS | V | |||
Resolution | 12 | Bits | ||||
Sample Rate | 200 | ksps | ||||
Offset | Internal 4.3V equivalent reference(2) | –0.24 | LSB | |||
Gain error | Internal 4.3V equivalent reference(2) | 7.14 | LSB | |||
DNL(4) | Differential nonlinearity | >–1 | LSB | |||
INL | Integral nonlinearity | ±4 | LSB | |||
ENOB | Effective number of bits | Internal 4.3V equivalent reference(2), 200 kSamples/s, 9.6kHz input tone | 9.8 | Bits | ||
Internal 4.3V equivalent reference(2), 200 kSamples/s, 9.6kHz input tone, DC/DC enabled | 9.8 | |||||
VDDS as reference, 200 kSamples/s, 9.6kHz input tone | 10.1 | |||||
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone | 11.1 | |||||
Internal reference, voltage scaling disabled, 14-bit mode, 200 kSamples/s, 600 Hz input tone (5) | 11.3 | |||||
Internal reference, voltage scaling disabled, 15-bit mode, 200 kSamples/s, 150 Hz input tone (5) | 11.6 | |||||
THD | Total harmonic distortion | Internal 4.3V equivalent reference(2), 200 kSamples/s, 9.6kHz input tone | –65 | dB | ||
VDDS as reference, 200 kSamples/s, 9.6kHz input tone | –70 | |||||
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone | –72 | |||||
SINAD, SNDR | Signal-to-noise and distortion ratio | Internal 4.3V equivalent reference(2), 200 kSamples/s, 9.6kHz input tone | 60 | dB | ||
VDDS as reference, 200 kSamples/s, 9.6kHz input tone | 63 | |||||
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone | 68 | |||||
SFDR | Spurious-free dynamic range | Internal 4.3V equivalent reference(2), 200 kSamples/s, 9.6kHz input tone | 70 | dB | ||
VDDS as reference, 200 kSamples/s, 9.6kHz input tone | 73 | |||||
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone | 75 | |||||
Conversion time | Serial conversion, time-to-output, 24MHz clock | 50 | Clock Cycles | |||
Current consumption | Internal 4.3V equivalent reference(2) | 0.42 | mA | |||
Current consumption | VDDS as reference | 0.6 | mA | |||
Reference voltage | Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1 | 4.3(2)(3) | V | |||
Reference voltage | Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3V) as follows: Vref = 4.3V × 1408 / 4095 | 1.48 | V | |||
Reference voltage | VDDS as reference, input voltage scaling enabled | VDDS | V | |||
Reference voltage | VDDS as reference, input voltage scaling disabled | VDDS / 2.82(3) | V | |||
Input impedance | 200 kSamples/s, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time | >1 | MΩ |