JAJSOS2B February 2021 – September 2022 CC2652PSIP
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | TYP | UNIT | |
---|---|---|---|---|
Core Current Consumption | ||||
Icore | Reset and Shutdown | Reset. nRESET pin asserted or VDDS below power-on-reset threshold(1) | 30 | µA |
Shutdown. No clocks running, no retention | 160 | nA | ||
Standby without cache retention |
RTC running, CPU, 80KB RAM and (partial) register retention. RCOSC_LF |
0.99 | µA | |
RTC running, CPU, 80KB RAM and (partial) register retention XOSC_LF |
1.15 | µA | ||
Standby with cache retention |
RTC running, CPU, 80KB RAM and (partial) register retention. RCOSC_LF |
3.36 | µA | |
RTC running, CPU, 80KB RAM and (partial) register retention. XOSC_LF |
3.47 | µA | ||
Idle | Supply Systems and RAM powered RCOSC_HF |
708 | µA | |
Active | MCU running CoreMark at 48 MHz RCOSC_HF |
3.5 | mA | |
Peripheral Current Consumption | ||||
Iperi | Peripheral power domain | Delta current with domain enabled | 102 | µA |
Serial power domain | Delta current with domain enabled | 7.56 | ||
RF Core | Delta current with power domain enabled, clock enabled, RF core idle |
221 | ||
µDMA | Delta current with clock enabled, module is idle | 67.1 | ||
Timers | Delta current with clock enabled, module is idle(4) | 85.1 | ||
I2C | Delta current with clock enabled, module is idle | 10.6 | ||
I2S | Delta current with clock enabled, module is idle | 27.6 | ||
SSI | Delta current with clock enabled, module is idle | 90.2 | ||
UART | Delta current with clock enabled, module is idle(2) | 175.9 | ||
CRYPTO (AES) | Delta current with clock enabled, module is idle(3) |
26.9 | ||
PKA | Delta current with clock enabled, module is idle |
88.9 | ||
TRNG | Delta current with clock enabled, module is idle |
37.4 | ||
Sensor Controller Engine Consumption | ||||
ISCE | Active mode | 24 MHz, infinite loop | 808 | µA |
Low-power mode | 2 MHz, infinite loop | 30.1 |