JAJSK09B November 2014 – September 2020 CC3100MOD
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Figure 8-8 shows the host SPI timing diagram.
PARAMETER NUMBER | DESCRIPTION | MIN | MAX | UNIT | |
---|---|---|---|---|---|
I1 | F(1) | Clock frequency at VBAT = 3.3 V | 20 | MHz | |
Clock frequency at VBAT ≤ 2.1 V | 12 | ||||
I2 | tclk(1)(2) | Clock period | 50 | ns | |
I5 | D(1) | Duty cycle | 45% | 55% | |
I6 | tIS(1) | RX data setup time | 4 | ns | |
I7 | tIH(1) | RX data hold time | 4 | ns | |
I8 | tOD(1) | TX data output delay | 20 | ns | |
I9 | tOH(1) | TX data hold time | 24 | ns |