4.11.2.1 nRESET (32K XTAL)

Figure 4-6 shows the reset timing diagram for the 32K XTAL first-time power-up and reset removal.

Table 4-2 First-Time Power-Up and Reset Removal Timing Requirements (32K XTAL)

4.11.2.2 nRESET (External 32K)

Figure 4-7 shows the reset timing diagram for the external 32K first-time power-up and reset removal.

Figure 4-7 First-Time Power-Up and Reset Removal Timing Diagram (External 32K)

Table 4-3 describes the timing requirements for the external 32K first-time power-up and reset removal.

4.11.2.3 Wakeup from Hibernate

Figure 4-8 shows the timing diagram for wakeup from the hibernate state.

Figure 4-8 Wakeup From Hibernate Timing Diagram

Table 4-4 describes the software hibernate timing requirements.

4.11.3.1 Slow Clock Using Internal Oscillator

The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance.

Figure 4-9 shows the crystal connections for the slow clock.

Figure 4-9 RTC Crystal Connections

4.11.3.2 Slow Clock Using an External Clock

When an RTC clock oscillator is present in the system, the CC3200 device can accept this clock directly as an input. The clock is fed on the RTC_XTAL_P line and the RTC_XTAL_N line is held to VIO. The clock must be a CMOS-level clock compatible with VIO fed to the device.

Figure 4-10 shows the external RTC clock input connection.

Figure 4-10 External RTC Clock Input

4.11.3.3 Fast Clock (F_ref) Using an External Crystal

The CC3200 device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The XTAL is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading capacitors.

Figure 4-11 shows the crystal connections for the fast clock.

Figure 4-11 Fast Clock Crystal Connections

4.11.3.4 Fast Clock (F_ref) Using an External Oscillator

The CC3200 device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the system.

If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the LDO improves noise on the TCXO power supply.

Figure 4-12 shows the connection.

Figure 4-12 External TCXO Input

Table 4-5 lists the external F_ref clock requirements.

4.11.3.5 Input Clocks/Oscillators

Table 4-6 lists the RTC crystal requirements.

Table 4-7 lists the external RTC digital clock requirements.

Table 4-8 lists the WLAN fast-clock crystal requirements.

4.11.3.6 WLAN Filter Requirements

The device requires an external bandpass filter to meet the various emission standards, including FCC. Table 4-9 presents the attenuation requirements for the bandpass filter. TI recommends using the same filter used in the reference design to ease the process of certification.

4.11.4.1 SPI

4.11.4.1.1 SPI Master

The CC3200 microcontroller includes one SPI module, which can be configured as a master or slave device. The SPI includes a serial clock with programmable frequency, polarity, and phase, a programmable timing control between chip select and external clock generation, and a programmable delay before the first SPI word is transmitted. Slave mode does not include a dead cycle between two successive words.

Figure 4-13 shows the timing diagram for the SPI master.

Figure 4-13 SPI Master Timing Diagram

Table 4-10 lists the timing parameters for the SPI master.

Table 4-10 SPI Master Timing Parameters

Parameter Number	Parameter(1)	Parameter Name	Min	Max	Unit
I1	F	Clock frequency		20	MHz
I2	Tclk	Clock period	50		ns
I5	D	Duty cycle	45	55	%
I6	tIS	RX data setup time	1		ns
I7	tIH	RX data hold time	2		ns
I8	tOD	TX data output delay		8.5	ns
I9	tOH	TX data hold time		8	ns

(1) Timing parameter assumes a maximum load of 20 pF.

4.11.4.1.2 SPI Slave

Figure 4-14 shows the timing diagram for the SPI slave.

Figure 4-14 SPI Slave Timing Diagram

Table 4-11 lists the timing parameters for the SPI slave.

Table 4-11 SPI Slave Timing Parameters

Parameter Number	Parameter(1)	Parameter Name	Min	Max	Unit
I1	F	Clock frequency @ VBAT = 3.3 V		20	MHz
		Clock frequency @ VBAT ≤ 2.1 V		12
I2	Tclk	Clock period	50		ns
I5	D	Duty cycle	45	55	%
I6	tIS	RX data setup time	4		ns
I7	tIH	RX data hold time	4		ns
I8	tOD	TX data output delay		20
I9	tOH	TX data hold time		24	ns

(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.

4.11.4.2 McASP

The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A fractional divider is available for bit-clock generation.

4.11.4.2.1 I2S Transmit Mode

Figure 4-15 shows the timing diagram for the I2S transmit mode.

Figure 4-15 I2S Transmit Mode Timing Diagram

Table 4-12 lists the timing parameters for the I2S transmit mode.

Table 4-12 I2S Transmit Mode Timing Parameters

Parameter Number	Parameter(1)	Parameter Name	Min	Max	Unit
I1	fclk	Clock frequency		9.216	MHz
I2	tLP	Clock low period		1/2 fclk	ns
I3	tHT	Clock high period		1/2 fclk	ns
I4	tOH	TX data hold time		22	ns

(1) Timing parameter assumes a maximum load of 20 pF.

4.11.4.2.2 I2S Receive Mode

Figure 4-16 shows the timing diagram for the I2S receive mode.

Figure 4-16 I2S Receive Mode Timing Diagram

Table 4-13 lists the timing parameters for the I2S receive mode.

Table 4-13 I2S Receive Mode Timing Parameters

Parameter Number	Parameter(1)	Parameter Name	Min	Max	Unit
I1	fclk	Clock frequency		9.216	MHz
I2	tLP	Clock low period		1/2 fclk	ns
I3	tHT	Clock high period		1/2 fclk	ns
I4	tOH	RX data hold time		0	ns
I5	tOS	RX data setup time		15	ns

(1) Timing parameter assumes a maximum load of 20 pF.

4.11.4.3 GPIO

All digital pins of the device can be used as general-purpose input/output (GPIO) pins.The GPIO module consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24 programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.

Figure 4-17 shows the GPIO timing diagram.

Figure 4-17 GPIO Timing

4.11.4.4 I²C

The CC3200 microcontroller includes one I²C module operating with standard (100 Kbps) or fast (400 Kbps) transmission speeds.

Figure 4-18 shows the I²C timing diagram.

Figure 4-18 I²C Timing

Table 4-17 lists the I²C timing parameters.

4.11.4.5 IEEE 1149.1 JTAG

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the IEEE Standard 1149.1,Test Access Port and Boundary- Scan Architecture.

Figure 4-19 shows the JTAG timing diagram.

Figure 4-19 JTAG Timing

Table 4-18 lists the JTAG timing parameters.

4.11.4.6 ADC

Table 4-19 lists the ADC electrical specifications.

Figure 4-20 shows the ADC clock timing diagram.

Figure 4-20 ADC Clock Timing

4.11.4.7 Camera Parallel Port

The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a FIFO, and generates DMA requests. The camera parallel port supports 8 bits.

Figure 4-21 shows the timing diagram for the camera parallel port.

Figure 4-21 Camera Parallel Port Timing Diagram

Table 4-20 lists the timing parameters for the camera parallel port.

4.11.4.8 UART

The CC3200 device includes two UARTs with the following features:

• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 16 x 8 TX and RX FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
• Fully programmable serial interface characteristics
  • 5, 6, 7, or 8 data bits
  • Even, odd, stick, or no-parity bit generation and detection
  • 1 or 2 stop-bit generation
• RTS and CTS hardware flow support
• Standard FIFO-level and End-of-Transmission interrupts
• Efficient transfers using μDMA
  • Separate channels for transmit and receive
  • Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level
  • Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level
• System clock is used to generate the baud clock.