JAJSE18E March   2017  – May 2021 CC3220MOD , CC3220MODA

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3220MODx and CC3220MODAx Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Module Pin Attributes
    3. 7.3 Connections for Unused Pins
    4. 7.4 Pin Attributes and Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip, but Before Reset Release
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption (CC3220MODS and CC3220MODAS)
    5. 8.5  Current Consumption (CC3220MODSF and CC3220MODASF)
    6. 8.6  TX Power and IBAT Versus TX Power Level Settings
    7. 8.7  Brownout and Blackout Conditions
    8. 8.8  Electrical Characteristics
    9. 8.9  CC3220MODAx Antenna Characteristics
    10. 8.10 WLAN Receiver Characteristics
    11. 8.11 WLAN Transmitter Characteristics
    12. 8.12 Reset Requirement
    13. 8.13 Thermal Resistance Characteristics for MOB and MON Packages
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power-Up Sequencing
      2. 8.14.2 Power-Down Sequencing
      3. 8.14.3 Device Reset
      4. 8.14.4 Wake Up From Hibernate Timing
      5. 8.14.5 Peripherals Timing
        1. 8.14.5.1  SPI
          1. 8.14.5.1.1 SPI Master
          2. 8.14.5.1.2 SPI Slave
        2. 8.14.5.2  I2S
          1. 8.14.5.2.1 I2S Transmit Mode
          2. 8.14.5.2.2 I2S Receive Mode
        3. 8.14.5.3  GPIOs
          1. 8.14.5.3.1 GPIO Input Transition Time Parameters
        4. 8.14.5.4  I2C
        5. 8.14.5.5  IEEE 1149.1 JTAG
        6. 8.14.5.6  ADC
        7. 8.14.5.7  Camera Parallel Port
        8. 8.14.5.8  UART
        9. 8.14.5.9  External Flash Interface
        10. 8.14.5.10 SD Host
        11. 8.14.5.11 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 プロセッサ・コア・サブシステム
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  Power-Management Subsystem
      1. 9.5.1 VBAT Wide-Voltage Connection
    6. 9.6  Low-Power Operating Mode
    7. 9.7  Memory
      1. 9.7.1 Internal Memory
        1. 9.7.1.1 SRAM
        2. 9.7.1.2 ROM
        3. 9.7.1.3 Flash Memory
        4. 9.7.1.4 Memory Map
    8. 9.8  Restoring Factory Default Configuration
    9. 9.9  Boot Modes
      1. 9.9.1 Boot Mode List
    10. 9.10 Device Certification and Qualification
      1. 9.10.1 FCC Certification and Statement
      2. 9.10.2 Industry Canada (IC) Certification and Statement
      3. 9.10.3 ETSI/CE Certification
      4. 9.10.4 MIC Certification
      5. 9.10.5 SRRC Certification and Statement
    11. 9.11 Module Markings
    12. 9.12 End Product Labeling
    13. 9.13 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Typical Application
    2. 10.2 Device Connection and Layout Fundamentals
      1. 10.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.2.2 Reset
      3. 10.2.3 Unused Pins
    3. 10.3 PCB Layout Guidelines
      1. 10.3.1 General Layout Recommendations
      2. 10.3.2 CC3220MODx RF Layout Recommendations
        1. 10.3.2.1 Antenna Placement and Routing
        2. 10.3.2.2 Transmission Line Considerations
      3. 10.3.3 CC3220MODAx RF Layout Recommendations
  11. 11Environmental Requirements and Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Development Tools and Software
    2. 12.2 Firmware Updates
    3. 12.3 Device Nomenclature
    4. 12.4 Documentation Support
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
        1. 13.2.2.1 CC3220MODx Tape Specifications
        2. 13.2.2.2 CC3220MODAx Tape Specifications

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • MON|63
サーマルパッド・メカニカル・データ

8.14.5.6 ADC

Table 8-13 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on using the ADC and for application-specific examples.

GUID-6D3DAD3A-97A5-4458-A0F7-0AEFE0C2BF61-low.gif Figure 8-15 ADC Clock Timing Diagram

 

Figure 8-15 shows the ADC clock timing diagram.

Table 8-13 ADC Electrical Specifications
PARAMETER DESCRIPTION TEST CONDITIONS / ASSUMPTIONS MIN TYP MAX UNIT
Nbits Number of bits 12 Bits
INL Integral nonlinearity Worst-case deviation from histogram method over full scale (not including first and last three LSB levels) –2.5 2.5 LSB
DNL Differential nonlinearity Worst-case deviation of any step from ideal –1 4 LSB
Input range 0 1.4 V
Driving source impedance 100 Ω
FCLK Clock rate Successive approximation input clock rate 10 MHz
Input capacitance 12 pF
Input impedance ADC Pin 57 2.15 kΩ
ADC Pin 58 0.7
ADC Pin 59 2.12
ADC Pin 60 1.17
Number of channels 4
Fsample Sampling rate of each pin 62.5 KSPS
F_input_max Maximum input signal frequency 31 kHz
SINAD Signal-to-noise and distortion Input frequency DC to 300 Hz and 1.4 Vpp sine wave input 55 60 dB
I_active Active supply current Average for analog-to-digital during conversion without reference current 1.5 mA
I_PD Power-down supply current for core supply Total for analog-to-digital when not active (this must be the SoC level test) 1 µA
Absolute offset error FCLK = 10 MHz ±2 mV
Gain error ±2%
Vref ADC reference voltage 1.467 V