JAJSMT4B February 2020 – May 2021 CC3230S , CC3230SF
PRODUCTION DATA
PARAMETER | DESCRIPTION | TEST CONDITIONS and ASSUMPTIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
Nbits | Number of bits | 12 | Bits | |||
INL | Integral nonlinearity | Worst-case deviation from histogram method over full scale (not including first and last three LSB levels) | –2.5 | 2.5 | LSB | |
DNL | Differential nonlinearity | Worst-case deviation of any step from ideal | –1 | 4 | LSB | |
Input range | 0 | 1.4 | V | |||
Driving source impedance | 100 | Ω | ||||
FCLK | Clock rate | Successive approximation input clock rate | 10 | MHz | ||
Input capacitance | 12 | pF | ||||
Input impedance | ADC Pin 57 | 2.15 | kΩ | |||
ADC Pin 58 | 0.7 | |||||
ADC Pin 59 | 2.12 | |||||
ADC Pin 60 | 1.17 | |||||
Number of channels | 4 | |||||
Fsample | Sampling rate of each pin | 62.5 | ksps | |||
F_input_max | Maximum input signal frequency | 31 | kHz | |||
SINAD | Signal-to-noise and distortion | Input frequency DC to 300 Hz and 1.4 Vpp sine wave input | 55 | 60 | dB | |
I_active | Active supply current | Average for analog-to-digital during conversion without reference current | 1.5 | mA | ||
I_PD | Power-down supply current for core supply | Total for analog-to-digital when not active (this must be the SoC level test) | 1 | µA | ||
Absolute offset error | FCLK = 10 MHz | ±2 | mV | |||
Gain error | ±2% | |||||
Vref | ADC reference voltage | 1.467 | V |