JAJSIK6C February   2020  – December 2024 CC3235MODAS , CC3235MODASF , CC3235MODS , CC3235MODSF

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 CC3235MODx and CC3235MODAx Pin Diagram
    2. 6.2 Pin Attributes and Pin Multiplexing
      1. 6.2.1 Module Pin Descriptions
    3. 6.3 Signal Descriptions
    4. 6.4 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    5. 6.5 Pad State After Application of Power to Chip, but Before Reset Release
    6. 6.6 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Current Consumption (CC3235MODS and CC3235MODAS)
      1.      21
      2.      22
    5. 7.5  Current Consumption (CC3235MODSF and CC3235MODASF)
      1.      24
      2.      25
    6. 7.6  TX Power Control for 2.4 GHz Band
    7. 7.7  TX Power Control for 5 GHz
    8. 7.8  Brownout and Blackout Conditions
    9. 7.9  Electrical Characteristics for GPIO Pins
      1. 7.9.1 Electrical Characteristics for Pin Internal Pullup and Pulldown (25°C)
    10. 7.10 CC3235MODAx Antenna Characteristics
    11. 7.11 WLAN Receiver Characteristics
      1.      33
      2.      34
    12. 7.12 WLAN Transmitter Characteristics
      1.      36
      2.      37
    13. 7.13 BLE and WLAN Coexistence Requirements
    14. 7.14 Reset Requirement
    15. 7.15 Thermal Resistance Characteristics for MOB and MON Packages
    16. 7.16 Timing and Switching Characteristics
      1. 7.16.1 Power-Up Sequencing
      2. 7.16.2 Power-Down Sequencing
      3. 7.16.3 Device Reset
      4. 7.16.4 Wake Up From Hibernate Timing
      5. 7.16.5 Peripherals Timing
        1. 7.16.5.1  SPI
          1. 7.16.5.1.1 SPI Master
          2. 7.16.5.1.2 SPI Slave
        2. 7.16.5.2  I2S
          1. 7.16.5.2.1 I2S Transmit Mode
          2. 7.16.5.2.2 I2S Receive Mode
        3. 7.16.5.3  GPIOs
          1. 7.16.5.3.1 GPIO Input Transition Time Parameters
        4. 7.16.5.4  I2C
        5. 7.16.5.5  IEEE 1149.1 JTAG
        6. 7.16.5.6  ADC
        7. 7.16.5.7  Camera Parallel Port
        8. 7.16.5.8  UART
        9. 7.16.5.9  External Flash Interface
        10. 7.16.5.10 SD Host
        11. 7.16.5.11 Timers
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Arm Cortex-M4 Processor Core Subsystem
    4. 8.4  Wi-Fi Network Processor Subsystem
      1. 8.4.1 WLAN
      2. 8.4.2 Network Stack
    5. 8.5  Security
    6. 8.6  FIPS 140-2 Level 1 Certification
    7. 8.7  Power-Management Subsystem
      1. 8.7.1 VBAT Wide-Voltage Connection
    8. 8.8  Low-Power Operating Mode
    9. 8.9  Memory
      1. 8.9.1 Internal Memory
        1. 8.9.1.1 SRAM
        2. 8.9.1.2 ROM
        3. 8.9.1.3 Flash Memory
        4. 8.9.1.4 Memory Map
    10. 8.10 Restoring Factory Default Configuration
    11. 8.11 Boot Modes
      1. 8.11.1 Boot Mode List
    12. 8.12 Hostless Mode
    13. 8.13 Device Certification and Qualification
      1. 8.13.1 FCC Certification and Statement
      2. 8.13.2 IC/ISED Certification and Statement
      3. 8.13.3 ETSI/CE Certification
      4. 8.13.4 MIC Certification
    14. 8.14 Module Markings
    15. 8.15 End Product Labeling
    16. 8.16 Manual Information to the End User
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 BLE/2.4GHz Radio Coexistence
      2. 9.1.2 Antenna Selection (CC3235MODx only)
      3. 9.1.3 Typical Application Schematic (CC3235MODx)
      4. 9.1.4 Typical Application Schematic (CC3235MODAx)
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 9.2.2 Reset
      3. 9.2.3 Unused Pins
    3. 9.3 PCB Layout Guidelines
      1. 9.3.1 General Layout Recommendations
      2. 9.3.2 CC3235MODx RF Layout Recommendations
        1. 9.3.2.1 Antenna Placement and Routing
        2. 9.3.2.2 Transmission Line Considerations
      3. 9.3.3 CC3235MODAx RF Layout Recommendations
  11. 10Environmental Requirements and SMT Specifications
    1. 10.1 PCB Bending
    2. 10.2 Handling Environment
      1. 10.2.1 Terminals
      2. 10.2.2 Falling
    3. 10.3 Storage Condition
      1. 10.3.1 Moisture Barrier Bag Before Opened
      2. 10.3.2 Moisture Barrier Bag Open
    4. 10.4 PCB Assembly Guide
      1. 10.4.1 PCB Land Pattern and Thermal Vias
      2. 10.4.2 SMT Assembly Recommendations
      3. 10.4.3 PCB Surface Finish Requirements
      4. 10.4.4 Solder Stencil
      5. 10.4.5 Package Placement
      6. 10.4.6 Solder Joint Inspection
      7. 10.4.7 Rework and Replacement
      8. 10.4.8 Solder Joint Voiding
    5. 10.5 Baking Conditions
    6. 10.6 Soldering and Reflow Condition
  12. 11Device and Documentation Support
    1. 11.1 Development Tools and Software
    2. 11.2 Firmware Updates
    3. 11.3 Device Nomenclature
    4. 11.4 Documentation Support
    5. 11.5 Related Links
    6. 11.6 サポート・リソース
    7. 11.7 Trademarks
    8. 11.8 静電気放電に関する注意事項
    9. 11.9 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
      3. 13.2.3 CC3235MODx Tape Specifications
      4. 13.2.4 CC3235MODAx Tape Specifications

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • MOB|63
サーマルパッド・メカニカル・データ
発注情報

6.2.1 Module Pin Descriptions

MODULE PINTYPE(1)CC3235 DEVICE PIN NO.MODULE PIN DESCRIPTION
NO.NAME
1GND––Ground
2GND––Ground
3GPIO10I/O1GPIO(2)
4GPIO11I/O2GPIO(2)
5GPIO14I/O5GPIO(2)
6GPIO15I/O6GPIO(2)
7GPIO16I/O7GPIO(2)
8GPIO17I/O8GPIO(2)
9GPIO12I/O3GPIO(2)
10GPIO13I/O4GPIO(2)
11GPIO22I/O15GPIO(2)
12JTAG_TDII/O16JTAG TDI input. Leave unconnected if not used on product(2)
13FLASH_SPI_MISOI–External serial flash programming: SPI data in
14FLASH_SPI_nCS_INI–External serial flash programming: SPI chip select (active low)
15FLASH_SPI_CLKI–External serial flash programming: SPI clock
16GND––Ground
17FLASH_SPI_MOSIO–External serial flash programming: SPI data out
18JTAG_TDOI/O17JTAG TDO output. Leave unconnected if not used on the product.(1)
19GPIO28I/O18GPIO(2)
20NC––No Connect
21JTAG_TCKI/O19JTAG TCK input. Leave unconnected if not used on the product.(2) An internal 100kΩ pulldown resistor is tied to this pin.
22JTAG_TMSI/O20JTAG TMS input. Leave unconnected if not used on the product.(2)
23SOP2–21An internal 100kΩ pulldown resistor is tied to this SOP pin. An external 10kΩ resistor is required to pull this pin high. See Section 8.11.1 for SOP[2:0] configuration modes.
24SOP1–34An internal 100kΩ pulldown resistor is tied to this SOP pin. An external 10kΩ resistor is required to pull this pin high. See Section 8.11.1 for SOP[2:0] configuration modes.
25GND––Ground
26GND––Ground
27GND––Ground
28GND––Ground
29GND––Ground
30GND––Ground
31CC3235MODx: RF ABG band
 CC3235MODAx: NC		I/O312.4GHz and 5 GHz RF input/output
32GND––Ground
33NC––No Connect
34SOP0–35An internal 100kΩ pulldown resistor is tied to this SOP pin. An external 10kΩ resistor is required to pull this pin high. See Section 8.11.1 for SOP[2:0] configuration modes.
35nRESETI32There is an internal, 100kΩ pullup resistor option from the nRESET pin to VBAT_RESET. Note: VBAT_RESET is not connected to VBAT1 or VBAT2 within the module. The following connection schemes are recommended:
  • Connect nRESET to a switch, external controller, or host, only if nRESET will be in a defined state under all operating conditions. Leave VBAT_RESET unconnected to save power.
  • If nRESET cannot be in a defined state under all operating conditions, connect VBAT_RESET to the main module power supply (VBAT1 and VBAT2). Due to the internal pullup resistor a leakage current of 3.3V / 100kΩ is expected.
36VBAT_RESET–37
37VBAT1Power39Power supply for the module, must be connected to battery (2.3V to 3.6V)
38GND––Ground
39NC–47No Connect
40VBAT2Power10, 44, 54Power supply for the module, must be connected to battery (2.3V to 3.6V)
41NC––No Connect
42GPIO30I/O53GPIO(2)
43GND––Ground
44GPIO0I/O50GPIO(2)
45NC––No Connect
46GPIO1I/O55GPIO(2)
47GPIO2I/O57GPIO(2)
48GPIO3I/O58GPIO(2)
49GPIO4I/O59GPIO(2)
50GPIO5I/O60GPIO(2)
51GPIO6I/O61GPIO(2)
52GPIO7I/O62GPIO(2)
53GPIO8I/O63GPIO(2)
54GPIO9I/O64GPIO(2)
55GND––Thermal ground
56GND––Thermal ground
57GND––Thermal ground
58GND––Thermal ground
59GND––Thermal ground
60GND––Thermal ground
61GND––Thermal ground
62GND––Thermal ground
63GND––Thermal ground
(1) I = input; O = output; I/O = bidirectional
(2) For pin multiplexing details, see Table 6-1.

 

 

The module makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at module reset) and register control.

The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used. Table 6-1 describes the general pin attributes and presents an overview of pin multiplexing. All pin multiplexing options are configurable using the pin MUX registers. The following special considerations apply:

  • All I/Os support drive strengths of 2mA, 4mA, and 6mA. Drive strength is individually configurable for each pin.
  • All I/Os support 10µA pullup and pulldown resistors.
  • By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
  • All digital I/Os are non-failsafe.

Note:

If an external device drives a positive voltage to the signal pads and the CC3235MODx or CC3235MODAx module is not powered, DC is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3235MODx or CC3235MODAx module can occur. To prevent current draw, TI recommends any one of the following conditions:

  • All devices interfaced to the CC3235MODx and CC3235MODAx modules must be powered from the same power rail as the chip.
  • Use level shifters between the device and any external devices fed from other independent rails.
  • The nRESET pin of the CC3235MODx and CC3235MODAx modules must be held low until the VBAT supply to the module is driven and stable.
  • All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.

The ADC inputs are tolerant up to 1.8 V (see Table 7-24 for more details about the usable range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 47], S8 [Pin 48], S9 [Pin 49], and S10 [Pin 50]). For more information, see Table 6-3.

Table 6-1 Pin Attributes and Pin Multiplexing
GENERAL PIN ATTRIBUTESFUNCTIONPAD STATES
Pkg. PinPin AliasUseSelect as Wakeup SourceConfig. Addl. Analog MuxMuxed With JTAGDig. Pin Mux Config. Reg.Dig. Pin Mux Config. Mode ValueSignal NameSignal DescriptionSignal DirectionLPDS(1)Hib(2)nRESET = 0
1GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
2GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
3GPIO10I/ONoNoNoGPIO_PAD_
CONFIG_10
(0x4402 E0C8)		0GPIO10GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
1I2C_SCLI2C clockI/O
(open drain)		Hi-Z,
Pull,
Drive
3GT_PWM06Pulse-width modulated O/POHi-Z,
Pull,
Drive
7UART1_TXUART TX dataO1
6SDCARD_CLKSD card clockO0
12GT_CCP01Timer capture portIHi-Z,
Pull,
Drive
4GPIO11I/OYesNoNoGPIO_PAD_
CONFIG_11
(0x4402 E0CC)		0GPIO11GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
1I2C_SDAI2C dataI/O
(open drain)		Hi-Z,
Pull,
Drive
3GT_PWM07Pulse-width modulated O/POHi-Z,
Pull,
Drive
4pXCLK (XVCLK)Free clock to parallel cameraO0
6SDCARD_CMDSD card command lineI/O
(open drain)		Hi-Z,
Pull,
Drive
7UART1_RXUART RX dataIHi-Z,
Pull,
Drive
12GT_CCP02Timer capture portIHi-Z,
Pull,
Drive
13MCAFSXI2S audio port frame syncOHi-Z,
Pull,
Drive
5GPIO14I/ONoNoNoGPIO_PAD_
CONFIG_14
(0x4402 E0D8)		0GPIO14GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
5I2C_SCLI2C clockI/O
(open drain)
7GSPI_CLKGeneral SPI clockI/O
4pDATA8 (CAM_D4)Parallel camera data bit 4I
12GT_CCP05Timer capture portI
6GPIO15I/ONoNoNoGPIO_PAD_
CONFIG_15
(0x4402 E0DC)		0GPIO15GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
5I2C_SDAI2C dataI/O
(open drain)
7GSPI_MISOGeneral SPI MISOI/O
4pDATA9 (CAM_D5)Parallel camera data bit 5I
13GT_CCP06Timer capture portI
8SDCARD_
DATA0		SD card dataI/O
7GPIO16I/ONoNoNoGPIO_PAD_
CONFIG_16
(0x4402 E0E0)		0GPIO16GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
7GSPI_MOSIGeneral SPI MOSII/OHi-Z,
Pull,
Drive
4pDATA10 (CAM_D6)Parallel camera data bit 6IHi-Z,
Pull,
Drive
5UART1_TXUART1 TX dataO1
13GT_CCP07Timer capture portIHi-Z,
Pull,
Drive
8SDCARD_CLKSD card clockOZero
8GPIO17I/OYesNoNoGPIO_PAD_
CONFIG_17
(0x4402 E0E4)		0GPIO17GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
5UART1_RXUART1 RX dataI
7GSPI_CSGeneral SPI chip selectI/O
4pDATA11 (CAM_D7)Parallel camera data bit 7I
8SDCARD_
CMD		SD card command lineI/O
9GPIO12I/ONoNoNoGPIO_PAD_
CONFIG_12
(0x4402 E0D0)		0GPIO12GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
3McACLKI2S audio port clock outputOHi-Z,
Pull,
Drive
4pVS (VSYNC)Parallel camera vertical syncIHi-Z,
Pull,
Drive
5I2C_SCLI2C clockI/O
(open drain)		Hi-Z,
Pull,
Drive
7UART0_TXUART0 TX dataO1
12GT_CCP03Timer capture portIHi-Z,
Pull,
Drive
10GPIO13I/OYesNoNoGPIO_PAD_
CONFIG_13
(0x4402 E0D4)		0GPIO13GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
5I2C_SDAI2C dataI/O
(open drain)
4pHS (HSYNC)Parallel camera horizontal syncI
7UART0_RXUART0 RX dataI
12GT_CCP04Timer capture portI
11GPIO22I/ONoNoNoGPIO_PAD_
CONFIG_22
(0x4402 E0F8)		0GPIO22GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
7McAFSXI2S audio port frame syncO
5GT_CCP04Timer capture portI
12JTAG_TDII/ONoNoMuxed with JTAG TDIGPIO_PAD_
CONFIG_23
(0x4402 E0FC)		1TDIJTAG TDI. Reset default pinout.IHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
0GPIO23GPIOI/O
2UART1_TXUART1 TX dataO1
9I2C_SCLI2C clockI/O
(open drain)		Hi-Z,
Pull,
Drive
13FLASH_
SPI_
MISO		N/AN/AN/AN/AN/AN/AFLASH_SPI_MISOData from SPI serial flash (fixed default)N/AHi-ZHi-ZHi-Z
14FLASH_
SPI_
nCS_IN		N/AN/AN/AN/AN/AN/AFLASH_SPI_nCS_INChip select to SPI serial flash (fixed default)N/A1Hi-Z,
Pull,
Drive		Hi-Z
15FLASH_
SPI_CLK		N/AN/AN/AN/AN/AN/AFLASH_SPI_
CLK		Clock to SPI serial flash (fixed default)N/AHi-Z,
Pull,
Drive(3)		Hi-Z,
Pull,
Drive		Hi-Z
16GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
17FLASH_
SPI_
MOSI		N/AN/AN/AN/AN/AN/AFLASH_SPI_MOSIData to SPI serial flash (fixed default)N/AHi-Z,
Pull,
Drive(3)		Hi-Z,
Pull,
Drive		Hi-Z
18JTAG_TDOI/OYesNoMuxed with JTAG TDOGPIO_PAD_
CONFIG_ 24
(0x4402 E100)		1TDOJTAG TDO. Reset default pinout.OHi-Z,
Pull,
Drive		Driven high in SWD; driven low in 4-wire JTAGHi-Z
0GPIO24GPIOI/O
5PWM0Pulse-width modulated O/PO
2UART1_RXUART1 RX dataI
9I2C_SDAI2C dataI/O
(open drain)
4GT_CCP06Timer capture portI
6McAFSXI2S audio port frame syncO
19GPIO28I/ONoNoNoGPIO_PAD_
CONFIG_ 40
(0x4402 E140)		0GPIO28GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
20NCWLAN analogN/AN/AN/AN/AN/ANCReservedN/AN/AN/AN/A
21JTAG_TCKI/ONoNoMuxed with JTAG/
SWD-TCK		GPIO_PAD_
CONFIG_ 28
(0x4402 E110)		1TCKJTAG/SWD TCK.
Reset default pinout.		IHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
8GT_PWM03Pulse-width modulated O/PO
22JTAG_TMSI/ONoNoMuxed with JTAG/
SWD-TMSC		GPIO_PAD_
CONFIG_ 29
(0x4402 E114)		1TMSJTAG/SWD TMS.
Reset default pinout.		I/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
0GPIO29GPIO
23(4)SOP2O onlyNoNoNoGPIO_PAD_
CONFIG_ 25
(0x4402 E104)		0GPIO25GPIOOHi-Z,
Pull,
Drive		Driven LowHi-Z
9GT_PWM02Pulse-width modulated O/POHi-Z,
Pull,
Drive
2McAFSXI2S audio port frame syncOHi-Z,
Pull,
Drive
See(5)TCXO_ENEnable to optional external 40-MHz TCXOO0
See(6)SOP2Sense-on-power 2IHi-Z,
Pull,
Drive
24SOP1Config senseN/AN/AN/AN/AN/ASOP1Sense-on-power 1N/AN/AN/AN/A
25GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
26GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
27GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
28GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
29GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
30GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
31RF_ABG
WLAN analogN/AN/AN/AN/AN/ACC3235MODx:
RF ABG band
 		N/AN/AN/AN/AN/A
32GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
33NCWLAN analogN/AN/AN/AN/ANCReserved
34SOP0Config senseN/AN/AN/AN/AN/ASOP0Sense-on-power 0N/AN/AN/AN/A
35nRESETGlobal resetN/AN/AN/AN/AN/AnRESETMaster chip reset. Active low.N/AN/AN/AN/A
36VBAT_
RESET		Global resetN/AN/AN/AN/AN/AVBAT_RESETVBAT to nRESET pullup resistorN/AN/AN/AN/A
37VBAT1Supply inputN/AN/AN/AN/AN/AVBAT1Analog DC/DC input (connected to chip input supply [VBAT])N/AN/AN/AN/A
38GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
39NCWLAN analogN/AN/AN/AN/AN/ANCReservedN/AN/AN/AN/A
40VBAT2Supply inputN/AN/AN/AN/AN/AVBAT2Analog input supply VBATN/AN/AN/AN/A
41NCWLAN analogN/AN/AN/AN/AN/ANCReservedN/AN/AN/AN/A
42GPIO30I/ONoUser config not required
(7)		NoGPIO_PAD_
CONFIG_30
(0x4402 E118)		0GPIO30GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
9UART0_TXUART0 TX dataO1
2McACLKI2S audio port clockOHi-Z,
Pull,
Drive
3McAFSXI2S audio port frame syncOHi-Z,
Pull,
Drive
4GT_CCP05Timer capture portIHi-Z,
Pull,
Drive
7GSPI_MISOGeneral SPI MISOI/OHi-Z,
Pull,
Drive
43GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
44GPIO0I/ONoUser config not required
(7)		NoGPIO_PAD_
CONFIG_0
(0x4402 E0A0)		0GPIO0GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
12UART0_CTSUART0 Clear-to-Send input (active low)IHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
6McAXR1I2S audio port data 1 (RX/TX)I/OHi-Z,
Pull,
Drive
7GT_CCP00Timer capture portIHi-Z,
Pull,
Drive
9GSPI_CSGeneral SPI chip selectI/OHi-Z,
Pull,
Drive
10UART1_RTSUART1 Request-to-Send (active low)O1
3UART0_RTSUART0 Request-to-Send (active low)O1
4McAXR0I2S audio port data 0 (RX/TX)I/OHi-Z,
Pull,
Drive
45NCWLAN analogN/AN/AN/AN/AN/ANCReservedN/AN/AN/AN/A
46GPIO1I/ONoNoNoGPIO_PAD_
CONFIG_1
(0x4402 E0A4)		0GPIO1GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
3UART0_TXUART0 TX dataO1
4pCLK (PIXCLK)Pixel clock from parallel camera sensorIHi-Z,
Pull,
Drive
6UART1_TXUART1 TX dataO1
7GT_CCP01Timer capture portIHi-Z,
Pull,
Drive
47(9)GPIO2Analog input (up to 1.8 V)/ digital I/OYesSee(8)NoGPIO_PAD_
CONFIG_2
(0x4402 E0A8)		See(5)ADC_CH0ADC channel 0 input (1.5-V max)IHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
0GPIO2GPIOI/OHi-Z,
Pull,
Drive
3UART0_RXUART0 RX dataIHi-Z,
Pull,
Drive
6UART1_RXUART1 RX dataIHi-Z,
Pull,
Drive
7GT_CCP02Timer capture portIHi-Z,
Pull,
Drive
48(9)GPIO3Analog input (up to 1.8 V)/ digital I/ONoSee(8)NoGPIO_PAD_
CONFIG_3
(0x4402 E0AC)		See(5)ADC_CH1ADC channel 1 input (1.5-V max)IHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
0GPIO3GPIOI/OHi-Z,
Pull,
Drive
6UART1_TXUART1 TX dataO1
4pDATA7 (CAM_D3)Parallel camera data bit 3IHi-Z,
Pull,
Drive
49(9)GPIO4Analog input (up to 1.8 V)/ digital I/OYesSee(8)YesGPIO_PAD_
CONFIG_4
(0x4402 E0B0)		See(5)ADC_CH2ADC channel 2 input (1.5-V max)IHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
0GPIO4GPIOI/OHi-Z,
Pull,
Drive
6UART1_RXUART1 RX dataIHi-Z,
Pull,
Drive
4pDATA6 (CAM_D2)Parallel camera data bit 2IHi-Z,
Pull,
Drive
50(9)GPIO5Analog input up to 1.5 VNoSee(8)NoGPIO_PAD_
CONFIG_5
(0x4402 E0B4)		See(5)ADC_CH3ADC channel 3 input (1.5 V max)Ii-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
0GPIO5GPIOI/OHi-Z,
Pull,
Drive
4pDATA5 (CAM_D1)Parallel camera data bit 1IHi-Z,
Pull,
Drive
6McAXR1I2S audio port data 1 (RX, TX)I/OHi-Z,
Pull,
Drive
7GT_CCP05Timer capture portIHi-Z,
Pull,
Drive
51GPIO6I/ONoNoNoGPIO_PAD_
CONFIG_6
(0x4402 E0B8)		0GPIO6GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
5UART0_RTSUART0 Request-to-Send (active low)O1
4pDATA4 (CAM_D0)Parallel camera data bit 0IHi-Z,
Pull,
Drive
3UART1_CTSUART1 Clear to send (active low)IHi-Z,
Pull,
Drive
6UART0_CTSUART0 Clear to send (active low)IHi-Z,
Pull,
Drive
7GT_CCP06Timer capture portIHi-Z,
Pull,
Drive
52GPIO7I/ONoNoNoGPIO_PAD_
CONFIG_7
(0x4402 E0BC)		0GPIO7GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
13McACLKI2S audio port clockOHi-Z,
Pull,
Drive
3UART1_RTSUART1 Request to send (active low)O1
10UART0_RTSUART0 Request to send (active low)O1
11UART0_TXUART0 TX dataO1
53GPIO8I/ONoNoNoGPIO_PAD_
CONFIG_8
(0x4402 E0C0)		0GPIO8GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
6SDCARD_IRQInterrupt from SD card (future support)I
7McAFSXI2S audio port frame syncO
12GT_CCP06Timer capture portI
54GPIO9I/ONoNoNoGPIO_PAD_
CONFIG_9
(0x4402 E0C4)		0GPIO9GPIOI/OHi-Z,
Pull,
Drive		Hi-Z,
Pull,
Drive		Hi-Z
3GT_PWM05Pulse-width modulated O/PO
6SDCARD_
DATA0		SD card dataI/O
7McAXR0I2S audio port data (RX, TX)I/O
12GT_CCP00Timer capture portI
55GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
56GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
57GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
58GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
59GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
60GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
61GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
62GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
63GNDGNDN/AN/AN/AN/AN/AGNDGNDN/AN/AN/AN/A
(1) LPDS state: The state of unused I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(2) Hibernate mode: The state of the I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(3) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldowns on FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(4) Pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TCXO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(6) Pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the chip hardware power-up mode. For this reason, the pin must be output only when used for digital functions.
(7) Device firmware automatically enables the digital path during ROM boot.
(8) Requires user configuration to enable the analog switch of the ADC channel. (The switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.
(9) Pin is shared by the ADC inputs and digital I/O pad cells.
Note:

The ADC inputs are tolerant up to 1.8V (see Section 7.16.5.6 for further details on the useable range of the ADC). The digital pads can tolerate up to 3.6V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 47], S8 [Pin 48], S9 [Pin 49], and S10 [Pin 50]). For more information, see Drive Strength and Reset States for Analog-Digital Multiplexed Pins.