JAJSGW3D April   2019  – May 2021 CC3235S , CC3235SF

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
      1.      11
    3. 7.3 Signal Descriptions
      1.      13
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Device, Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3235S)
      1.      24
      2.      25
    6. 8.6  Current Consumption Summary (CC3235SF)
      1.      27
      2.      28
    7. 8.7  TX Power Control for 2.4 GHz Band
    8. 8.8  TX Power Control for 5 GHz
    9. 8.9  Brownout and Blackout Conditions
    10. 8.10 Electrical Characteristics for GPIO Pins
      1.      33
      2.      34
    11. 8.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 8.12 WLAN Receiver Characteristics
      1.      37
      2.      38
    13. 8.13 WLAN Transmitter Characteristics
      1.      40
      2.      41
    14. 8.14 WLAN Transmitter Out-of-Band Emissions
      1.      43
      2.      44
    15. 8.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 8.16 Thermal Resistance Characteristics for RGK Package
    17. 8.17 Timing and Switching Characteristics
      1. 8.17.1 Power Supply Sequencing
      2. 8.17.2 Device Reset
      3. 8.17.3 Reset Timing
        1. 8.17.3.1 nRESET (32-kHz Crystal)
        2.       52
        3.       53
        4. 8.17.3.2 nRESET (External 32-kHz Clock)
          1.        55
      4. 8.17.4 Wakeup From HIBERNATE Mode
      5. 8.17.5 Clock Specifications
        1. 8.17.5.1 Slow Clock Using Internal Oscillator
        2. 8.17.5.2 Slow Clock Using an External Clock
          1.        60
        3. 8.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        62
        4. 8.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        64
      6. 8.17.6 Peripherals Timing
        1. 8.17.6.1  SPI
          1. 8.17.6.1.1 SPI Master
            1.         68
          2. 8.17.6.1.2 SPI Slave
            1.         70
        2. 8.17.6.2  I2S
          1. 8.17.6.2.1 I2S Transmit Mode
            1.         73
          2. 8.17.6.2.2 I2S Receive Mode
            1.         75
        3. 8.17.6.3  GPIOs
          1. 8.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1.         78
          2. 8.17.6.3.2 GPIO Input Transition Time Parameters
            1.         80
        4. 8.17.6.4  I2C
          1.        82
        5. 8.17.6.5  IEEE 1149.1 JTAG
          1.        84
        6. 8.17.6.6  ADC
          1.        86
        7. 8.17.6.7  Camera Parallel Port
          1.        88
        8. 8.17.6.8  UART
        9. 8.17.6.9  SD Host
        10. 8.17.6.10 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  FIPS 140-2 Level 1 Certification
    6. 9.6  Power-Management Subsystem
    7. 9.7  Low-Power Operating Mode
    8. 9.8  Memory
      1. 9.8.1 External Memory Requirements
      2. 9.8.2 Internal Memory
        1. 9.8.2.1 SRAM
        2. 9.8.2.2 ROM
        3. 9.8.2.3 Flash Memory
        4. 9.8.2.4 Memory Map
    9. 9.9  Restoring Factory Default Configuration
    10. 9.10 Boot Modes
      1. 9.10.1 Boot Mode List
    11. 9.11 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1  Third-Party Products Disclaimer
    2. 11.2  Tools and Software
    3. 11.3  Firmware Updates
    4. 11.4  Device Nomenclature
    5. 11.5  Documentation Support
    6. 11.6  Related Links
    7. 11.7  サポート・リソース
    8. 11.8  Trademarks
    9. 11.9  Electrostatic Discharge Caution
    10. 11.10 Export Control Notice
    11. 11.11 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
      1. 12.1.1 Package Option Addendum
        1. 12.1.1.1 Packaging Information
        2. 12.1.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Table 7-3 Signal Descriptions
FUNCTION SIGNAL NAME PIN
NO.		 PIN
TYPE		 SIGNAL DIRECTION DESCRIPTION
ADC ADC_CH0 57 I/O I ADC channel 0 input (maximum of 1.5 V)
ADC_CH1 58 I/O I ADC channel 1 input (maximum of 1.5 V)
ADC_CH2 59 I/O I ADC channel 2 input (maximum of 1.5 V)
ADC_CH3 60 I I ADC channel 3 input (maximum of 1.5 V)
Antenna selection GPIO10 1 I/O O Antenna selection control
GPIO11 2 I/O O
GPIO12 3 I/O O
GPIO13 4 I/O O
GPIO14 5 I/O O
GPIO15 6 I/O O
GPIO16 7 I/O O
GPIO17 8 I/O O
GPIO22 15 I/O O
GPIO28 18(1) I/O O
GPIO25 21 O O
GPIO31 45(1)(2) I/O O
GPIO0 50 I/O O
GPIO32 52(1) I/O O
GPIO30 53(1) I/O O
GPIO3 58 I/O O
GPIO4 59 I/O O
GPIO5 60 I/O O
GPIO6 61 I/O O
GPIO8 63 I/O O
GPIO9 64 I/O O
BLE/2.4 GHz radio coexistence GPIO10 1 I/O I/O Coexistence inputs and outputs
GPIO11 2 I/O O
GPIO12 3 I/O I/O
GPIO13 4 I/O I/O
GPIO14 5 I/O I/O
GPIO15 6 I/O I/O
GPIO16 7 I/O I/O
GPIO17 8 I/O O
GPIO22 15 I/O I/O
GPIO28 18(1) I/O I/O
GPIO25 21 O O
GPIO31 45(1)(2) I/O I/O
GPIO0 50 I/O I/O
GPIO32 52(1) I/O I/O
GPIO30 53(1) I/O I/O
GPIO3 58 I/O O
GPIO4 59 I/O O
GPIO5 60 I/O I/O
GPIO6 61 I/O I/O
GPIO8 63 I/O I/O
GPIO9 64 I/O I/O
Clock WLAN_XTAL_N 22 — — 40-MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P 23 — — 40-MHz crystal or TCXO clock input
RTC_XTAL_P 51 — — Connect 32.768-kHz crystal or force external CMOS level clock
RTC_XTAL_N 52 — — Connect 32.768-kHz crystal or connect 100-kΩ resistor to supply voltage
Hostless mode HM_IO 1 I/O I/O Hostless mode inputs and outputs
2 I/O O
3 I/O I/O
4 I/O I/O
5 I/O I/O
6 I/O I/O
7 I/O I/O
8 I/O O
15 I/O I/O
18(1) I/O I/O
21 O O
45(1)(2) I/O I/O
50 I/O I/O
52(1) I/O I/O
53(1) I/O I/O
58 O O
59 O O
60 I/O I/O
61 I/O I/O
63 I/O I/O
64 I/O I/O
JTAG / SWD TDI 16 I/O I JTAG TDI. Reset default pinout.
TDO 17 I/O O JTAG TDO. Reset default pinout.
TCK 19 I/O I JTAG/SWD TCK. Reset default pinout.
TMS 20 I/O I/O JTAG/SWD TMS. Reset default pinout.
I2C I2C_SCL 1 I/O I/O (open drain) I2C clock data
3
5
16
I2C_SDA 2 I/O I/O (open drain) I2C data
4
6
17
Timers GT_PWM06 1 I/O O Pulse-width modulated O/P
GT_CCP01 1 I/O I Timer capture port
GT_PWM07 2 I/O O Pulse-width modulated O/P
GT_CCP02 2 I/O I Timer capture ports
GT_CCP03 3 I/O I
GT_CCP04 4 I/O I
15 I/O I
GT_CCP05 5 I/O I
GT_CCP06 6 I/O I
17 I/O I
61 I/O I
63 I/O I
GT_CCP07 7 I/O I
PWM0 17 I/O O Pulse-width modulated outputs
GT_PWM03 19 I/O O
GT_PWM02 21 O O
GT_CCP00 50 I/O I Timer capture ports
64 I/O I
GT_CCP05 53 I/O I
GT_CCP01 55 I/O I
GT_CCP02 57 I/O I
GT_CCP05 60 I I Timer capture port Input
GT_PWM05 64 I/O O Pulse-width modulated output
GPIO GPIO10 1 I/O I/O General-purpose inputs or outputs
GPIO11 2 I/O I/O
GPIO12 3 I/O I/O
GPIO13 4 I/O I/O
GPIO14 5 I/O I/O
GPIO15 6 I/O I/O
GPIO16 7 I/O I/O
GPIO17 8 I/O I/O
GPIO22 15 I/O I/O
GPIO23 16 I/O I/O
GPIO24 17 I/O I/O
GPIO28 18 I/O I/O
GPIO29 20 I/O I/O
GPIO25 21 O O
GPIO31 45(2) I/O I/O
GPIO0 50 I/O I/O
GPIO32 52 I/O O
GPIO30 53 I/O I/O
GPIO1 55 I/O I/O
GPIO2 57 I/O I/O
GPIO3 58 I/O I/O
GPIO4 59 I/O I/O
GPIO5 60 I/O I/O
GPIO6 61 I/O I/O
GPIO7 62 I/O I/O
GPIO8 63 I/O I/O
GPIO9 64 I/O I/O
McASP
I2S or PCM		 MCAFSX 2 I/O O I2S audio port frame sync
15
17
21
45(2)
53
63
McACLK 3 I/O O I2S audio port clock outputs
52 O O
53 I/O O
McAXR1 50 I/O I/O I2S audio port data 1 (RX/TX)
60 I I/O I2S audio port data 1 (RX and TX)
McAXR0 45(2) I/O I/O I2S audio port data 0 (RX and TX)
50 I/O I/O
52 O O I2S audio port data (only output mode is supported on pin 52)
64 I/O I/O I2S audio port data (RX and TX)
McACLKX 62 I/O O I2S audio port clock
Multimedia card
(MMC or SD)		 SDCARD_CLK 1 I/O O SD card clock data
7
SDCARD_CMD 2 I/O I/O (open drain) SD card command line
8 I/O I/O
SDCARD_DATA0 6 I/O I/O SD card data
64
SDCARD_IRQ 63 I/O I Interrupt from SD card(3)
Parallel interface
(8-bit π)		 pXCLK (XVCLK) 2 I/O O Free clock to parallel camera
pVS (VSYNC) 3 I/O I Parallel camera vertical sync
pHS (HSYNC) 4 I/O I Parallel camera horizontal sync
pDATA8 (CAM_D4) 5 I/O I Parallel camera data bit 4
pDATA9 (CAM_D5) 6 I/O I Parallel camera data bit 5
pDATA10 (CAM_D6) 7 I/O I Parallel camera data bit 6
pDATA11 (CAM_D7) 8 I/O I Parallel camera data bit 7
pCLK (PIXCLK) 55 I/O I Pixel clock from parallel camera sensor
pDATA7 (CAM_D3) 58 I/O I Parallel camera data bit 3
pDATA6 (CAM_D2) 59 I/O I Parallel camera data bit 2
pDATA5 (CAM_D1) 60 I I Parallel camera data bit 1
pDATA4 (CAM_D0) 61 I/O I Parallel camera data bit 0
Power VDD_DIG1 9 — — Internal digital core voltage
VIN_IO1 10 — — Device supply voltage (VBAT)
VDD_PLL 24 — — Internal analog voltage
LDO_IN2 25 — — Internal analog RF supply from analog DC/DC output
VDD_PA_IN 33 — — Internal PA supply voltage from PA DC/DC output
LDO_IN1 36 — — Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA 37 — — Analog DC/DC input (connected to device input supply [VBAT])
DCDC_ANA_SW 38 — — Internal analog DC/DC switching node
VIN_DCDC_PA 39 — — PA DC/DC input (connected to device input supply [VBAT])
DCDC_PA_SW_P 40 — — Internal PA DC/DC switching node
DCDC_PA_SW_N 41 — — Internal PA DC/DC switching node
DCDC_PA_OUT 42 — — Internal PA buck converter output
DCDC_DIG_SW 43 — — Internal digital DC/DC switching node
VIN_DCDC_DIG 44 — — Digital DC/DC input (connected to device input supply [VBAT])
DCDC_ANA2_SW_P 45(2) — — Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N 46 — — Internal analog to DC/DC converter –ve switching node
VDD_ANA2 47 — — Internal analog to DC/DC output
VDD_ANA1 48 — — Internal analog supply fed by ANA2 DC/DC output
VDD_RAM 49 — — Internal SRAM LDO output
VIN_IO2 54 — — Device supply voltage (VBAT)
VDD_DIG2 56 — — Internal digital core voltage
Reset nRESET 32 I I Global master device reset (active low)
RF A_RX 27 I I WLAN analog A-band receive
A_TX 28 O O WLAN analog A-band transmit
RF_BG 31 I/O I/O WLAN analog RF 802.11 b/g bands
SPI GSPI_CLK 5 I/O I/O General SPI clock
45(2) I/O I/O
GSPI_MISO 6 I/O I/O General SPI MISO
53 I/O I/O
GSPI_CS 8 I/O I/O General SPI device select
50 I/O I/O
GSPI_MOSI 7 I/O I/O General SPI MOSI
52 O O
FLASH SPI FLASH_SPI_CLK 11 O O Clock to SPI serial flash (fixed default)
FLASH_SPI_DOUT 12 O O Data to SPI serial flash (fixed default)
FLASH_SPI_DIN 13 I I Data from SPI serial flash (fixed default)
FLASH_SPI_CS 14 O O Device select to SPI serial flash (fixed default)
UART UART1_TX 1 I/O O UART TX data
7 I/O O
16 I/O O
55 I/O O
58 I/O O UART1 TX data
UART1_RX 2 I/O I UART RX data
8 I/O I
17 I/O I
45(2) I/O I
57 I/O I UART1 RX data
59 I/O I
UART1_RTS 50 I/O O UART1 request-to-send (active low)
62 I/O O
UART1_CTS 61 I/O I UART1 clear-to-send (active low)
UART0_TX 3 I/O O UART0 TX data
53 I/O O
55 I/O O
62 I/O O
UART0_RX 4 I/O I UART0 RX data
45(2) I/O I
57 I/O I UART0 RX data
UART0_CTS 50 I/O I UART0 clear-to-send input (active low)
61
UART0_RTS 50 I/O O UART0 request-to-send (active low)
52 O O
61 I/O O
62 I/O O
Sense-On-Power SOP2 21(4) O I Sense-on-power 2
SOP1 34 I I Configuration sense-on-power 1
SOP0 35 I I Configuration sense-on-power 0
(1) LPDS retention unavailable.
(2) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(3) Future support.
(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.