JAJSGW3E April   2019  – December 2024 CC3235S , CC3235SF

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
    4. 6.4 Pin Multiplexing
    5. 6.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 6.6 Pad State After Application of Power to Device, Before Reset Release
    7. 6.7 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Current Consumption Summary (CC3235S)
      1.      24
      2.      25
    6. 7.6  Current Consumption Summary (CC3235SF)
      1.      27
      2.      28
    7. 7.7  TX Power Control for 2.4 GHz Band
    8. 7.8  TX Power Control for 5 GHz
    9. 7.9  Brownout and Blackout Conditions
    10. 7.10 Electrical Characteristics for GPIO Pins
      1.      33
      2.      34
    11. 7.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 7.12 WLAN Receiver Characteristics
      1.      37
      2.      38
    13. 7.13 WLAN Transmitter Characteristics
      1.      40
      2.      41
    14. 7.14 WLAN Transmitter Out-of-Band Emissions
      1.      43
      2.      44
    15. 7.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 7.16 Thermal Resistance Characteristics for RGK Package
    17. 7.17 Timing and Switching Characteristics
      1. 7.17.1 Power Supply Sequencing
      2. 7.17.2 Device Reset
      3. 7.17.3 Reset Timing
        1. 7.17.3.1 nRESET (32kHz Crystal)
        2.       52
        3.       53
        4. 7.17.3.2 nRESET (External 32kHz Clock)
          1.        55
      4. 7.17.4 Wakeup From HIBERNATE Mode
      5. 7.17.5 Clock Specifications
        1. 7.17.5.1 Slow Clock Using Internal Oscillator
        2. 7.17.5.2 Slow Clock Using an External Clock
          1.        60
        3. 7.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        62
        4. 7.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        64
      6. 7.17.6 Peripherals Timing
        1. 7.17.6.1  SPI
          1. 7.17.6.1.1 SPI Master
            1.         68
          2. 7.17.6.1.2 SPI Slave
            1.         70
        2. 7.17.6.2  I2S
          1. 7.17.6.2.1 I2S Transmit Mode
            1.         73
          2. 7.17.6.2.2 I2S Receive Mode
            1.         75
        3. 7.17.6.3  GPIOs
          1. 7.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3V)
            1.         78
          2. 7.17.6.3.2 GPIO Input Transition Time Parameters
            1.         80
        4. 7.17.6.4  I2C
          1.        82
        5. 7.17.6.5  IEEE 1149.1 JTAG
          1.        84
        6. 7.17.6.6  ADC
          1.        86
        7. 7.17.6.7  Camera Parallel Port
          1.        88
        8. 7.17.6.8  UART
        9. 7.17.6.9  SD Host
        10. 7.17.6.10 Timers
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 8.3  Wi-Fi® Network Processor Subsystem
      1. 8.3.1 WLAN
      2. 8.3.2 Network Stack
    4. 8.4  Security
    5. 8.5  FIPS 140-2 Level 1 Certification
    6. 8.6  Power-Management Subsystem
    7. 8.7  Low-Power Operating Mode
    8. 8.8  Memory
      1. 8.8.1 External Memory Requirements
      2. 8.8.2 Internal Memory
        1. 8.8.2.1 SRAM
        2. 8.8.2.2 ROM
        3. 8.8.2.3 Flash Memory
        4. 8.8.2.4 Memory Map
    9. 8.9  Restoring Factory Default Configuration
    10. 8.10 Boot Modes
      1. 8.10.1 Boot Mode List
    11. 8.11 Hostless Mode
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
      1. 9.1.1 BLE/2.4GHz Radio Coexistence
      2. 9.1.2 Antenna Selection
      3. 9.1.3 Typical Application
    2. 9.2 PCB Layout Guidelines
      1. 9.2.1 General PCB Guidelines
      2. 9.2.2 Power Layout and Routing
        1. 9.2.2.1 Design Considerations
      3. 9.2.3 Clock Interface Guidelines
      4. 9.2.4 Digital Input and Output Guidelines
      5. 9.2.5 RF Interface Guidelines
  11. 10Device and Documentation Support
    1. 10.1  サード・パーティ製品に関する免責事項
    2. 10.2  Tools and Software
    3. 10.3  Firmware Updates
    4. 10.4  Device Nomenclature
    5. 10.5  Documentation Support
    6. 10.6  Related Links
    7. 10.7  サポート・リソース
    8. 10.8  Trademarks
    9. 10.9  静電気放電に関する注意事項
    10. 10.10 Export Control Notice
    11. 10.11 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
      1. 12.1.1 Packaging Option Addendum

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

8.7 Low-Power Operating Mode

From a power-management perspective, the CC3235x device comprises the following two independent subsystems:

  • Arm® Cortex®-M4 application processor subsystem
  • Networking subsystem

Each subsystem operates in one of several power states.

The Arm® Cortex®-M4 application processor runs the user application loaded from an external serial flash or internal flash (in CC3235SF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer functions.

The user program controls the power state of the application processor subsystem. The application processor can be in one of the five modes described in Table 8-2.

Table 8-2 User Program Modes
APPLICATION PROCESSOR (MCU) MODE(1)DESCRIPTION
MCU active modeMCU executing code at a state rate of 80MHz
MCU sleep modeThe MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity from any GPIO line or peripheral.
MCU LPDS modeState information is lost and only certain MCU-specific register configurations are retained. The MCU can wake up from external events or by using an internal timer. (The wake-up time is less than 3ms.) Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the wake-up source.
MCU hibernate modeThe lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly powered by the input supply is retained. The RTC continues running and the MCU supports wakeup from an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15ms plus the time to load the application from serial flash, which varies according to code size. In this mode, the MCU can be configured to wake up using the RTC timer or external event on a GPIO.
MCU shutdown modeThe lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in this mode is longer than hibernate at about 1.1s. To enter or exit the shutdown mode, the state of the nRESET line is changed (low to shut down, high to turn on).
(1) Modes are listed in order of power consumption, with the highest power modes listed first.

 

The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network activity, the NWP sleeps most of the time and wakes up only for beacon reception (see
Table 8-3).

Table 8-3 Networking Subsystem Modes
NETWORK PROCESSOR MODEDESCRIPTION
Network active mode
(processing layer 3, 2, and 1)		Transmitting or receiving IP protocol packets
Network active mode
(processing layer 2 and 1)		Transmitting or receiving MAC management frames; IP processing is not required.
Network active listen modeSpecial power-optimized active mode for receiving beacon frames (no other frames are supported)
Network connected IdleA composite mode that implements 802.11 infrastructure power-save operation. The CC3235x NWP automatically enters LPDS mode between beacons and then wakes into active listen mode to receive a beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS mode and the cycle repeats.
Advanced features of long sleep interval and IoT low power for extending LPDS time for up to 22 seconds while maintaining Wi-Fi connection is supported in this mode.
Network LPDS modeLow-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake-up.
Network disabledThe network is disabled.

The operation of the application and network processor ensures that the device remains in the lowest power mode most of the time to preserve battery life.

The following examples show the use of the power modes in applications:

  • A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but sends and receives little data spends most of the time in connected idle, which is a composite of receiving a beacon frame and waiting for the next beacon.
  • A product that is not continuously connected to the network but instead wakes up periodically (for example, every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to transmit data.