JAJSGW3E April   2019  – December 2024 CC3235S , CC3235SF

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
    4. 6.4 Pin Multiplexing
    5. 6.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 6.6 Pad State After Application of Power to Device, Before Reset Release
    7. 6.7 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Current Consumption Summary (CC3235S)
      1.      24
      2.      25
    6. 7.6  Current Consumption Summary (CC3235SF)
      1.      27
      2.      28
    7. 7.7  TX Power Control for 2.4 GHz Band
    8. 7.8  TX Power Control for 5 GHz
    9. 7.9  Brownout and Blackout Conditions
    10. 7.10 Electrical Characteristics for GPIO Pins
      1.      33
      2.      34
    11. 7.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 7.12 WLAN Receiver Characteristics
      1.      37
      2.      38
    13. 7.13 WLAN Transmitter Characteristics
      1.      40
      2.      41
    14. 7.14 WLAN Transmitter Out-of-Band Emissions
      1.      43
      2.      44
    15. 7.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 7.16 Thermal Resistance Characteristics for RGK Package
    17. 7.17 Timing and Switching Characteristics
      1. 7.17.1 Power Supply Sequencing
      2. 7.17.2 Device Reset
      3. 7.17.3 Reset Timing
        1. 7.17.3.1 nRESET (32kHz Crystal)
        2.       52
        3.       53
        4. 7.17.3.2 nRESET (External 32kHz Clock)
          1.        55
      4. 7.17.4 Wakeup From HIBERNATE Mode
      5. 7.17.5 Clock Specifications
        1. 7.17.5.1 Slow Clock Using Internal Oscillator
        2. 7.17.5.2 Slow Clock Using an External Clock
          1.        60
        3. 7.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        62
        4. 7.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        64
      6. 7.17.6 Peripherals Timing
        1. 7.17.6.1  SPI
          1. 7.17.6.1.1 SPI Master
            1.         68
          2. 7.17.6.1.2 SPI Slave
            1.         70
        2. 7.17.6.2  I2S
          1. 7.17.6.2.1 I2S Transmit Mode
            1.         73
          2. 7.17.6.2.2 I2S Receive Mode
            1.         75
        3. 7.17.6.3  GPIOs
          1. 7.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3V)
            1.         78
          2. 7.17.6.3.2 GPIO Input Transition Time Parameters
            1.         80
        4. 7.17.6.4  I2C
          1.        82
        5. 7.17.6.5  IEEE 1149.1 JTAG
          1.        84
        6. 7.17.6.6  ADC
          1.        86
        7. 7.17.6.7  Camera Parallel Port
          1.        88
        8. 7.17.6.8  UART
        9. 7.17.6.9  SD Host
        10. 7.17.6.10 Timers
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 8.3  Wi-Fi® Network Processor Subsystem
      1. 8.3.1 WLAN
      2. 8.3.2 Network Stack
    4. 8.4  Security
    5. 8.5  FIPS 140-2 Level 1 Certification
    6. 8.6  Power-Management Subsystem
    7. 8.7  Low-Power Operating Mode
    8. 8.8  Memory
      1. 8.8.1 External Memory Requirements
      2. 8.8.2 Internal Memory
        1. 8.8.2.1 SRAM
        2. 8.8.2.2 ROM
        3. 8.8.2.3 Flash Memory
        4. 8.8.2.4 Memory Map
    9. 8.9  Restoring Factory Default Configuration
    10. 8.10 Boot Modes
      1. 8.10.1 Boot Mode List
    11. 8.11 Hostless Mode
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
      1. 9.1.1 BLE/2.4GHz Radio Coexistence
      2. 9.1.2 Antenna Selection
      3. 9.1.3 Typical Application
    2. 9.2 PCB Layout Guidelines
      1. 9.2.1 General PCB Guidelines
      2. 9.2.2 Power Layout and Routing
        1. 9.2.2.1 Design Considerations
      3. 9.2.3 Clock Interface Guidelines
      4. 9.2.4 Digital Input and Output Guidelines
      5. 9.2.5 RF Interface Guidelines
  11. 10Device and Documentation Support
    1. 10.1  サード・パーティ製品に関する免責事項
    2. 10.2  Tools and Software
    3. 10.3  Firmware Updates
    4. 10.4  Device Nomenclature
    5. 10.5  Documentation Support
    6. 10.6  Related Links
    7. 10.7  サポート・リソース
    8. 10.8  Trademarks
    9. 10.9  静電気放電に関する注意事項
    10. 10.10 Export Control Notice
    11. 10.11 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
      1. 12.1.1 Packaging Option Addendum

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

9.1.3 Typical Application

Figure 9-7 shows the schematic of the engine area for the CC3235x device in the wide-voltage mode of operation, with the corresponding bill of materials show in Table 9-1. Figure 9-8 provides the schematic for the RF implementation with and without BLE/2.4GHz coexistence, with the corresponding bill of materials shown in Table 9-2. For a full operation reference design, see the CC3235x SimpleLink™ and Internet of Things Hardware Design Files.

CC3235S CC3235SF CC3235x Engine AreaFigure 9-7 CC3235x Engine Area
Table 9-1 Bill of Materials for CC3235x Engine Area
QuantityDesignatorValueManufacturerPart NumberDescription
2C1, C2100 µFTaiyo YudenLMK325ABJ107MMHTCAP, CERM, 100 µF, 10 V,
+/- 20%, X5R, AEC-Q200 Grade 3, 1210
3C3, C4, C64.7 µFTaiyo YudenJMK105BC6475MV-FCAP, CERM, 4.7 uF, 6.3 V,
+/- 20%, X6S, 0402
3C5, C16, C290.6 pFMuRataGJM0335C1ER60BB01DCAP, CERM, 0.6pF, 25 V,
+/- 16%, C0G/NP0, 0201
1C70.5 pFMurataGJM0335C1ER50BB01DCAP, CERM, 0.5 pF, 25 V,
+/- 20%, C0G/NP0, 0201
7C8, C9, C11, C13, C21, C22, C240.1 µFWalsinCL05B104KO5NNNCCAP, CERM, 0.1 µF, 16 V,
+/- 10%, X7R, 0402
1C100.01 µFWalsin0402B103K500CTCAP, CERM, 0.01 µF, 50 V,
+/- 10%, X7R, 0402
3C12, C20, C2310 µFTaiyo YudenLMK107BC6106MA-TCAP, CERM, 10 uF, 10 V,
+/- 20%, X6S, 0603
1C140.2 pFMuRataGJM0335C1ER20BB01DCAP, CERM, 0.2pF, 25 V,
+/- 50%, C0G/NP0, 0201
2C15, C250.1 µFSamsung Electro-MechanicsCL03A104KP3NNNCCAP, CERM, 0.1 uF, 10 V,
+/- 10%, X5R, 0201
2C17, C1822 µFMuRataGRM188C80G226ME15JCAP, CERM, 22 uF, 4 V,
+/- 20%, X6S, 0603
1C191 µFWalsinCL05A105MP5NNNCCAP, CERM, 1 µF, 10 V,
+/- 20%, X5R, 0402
2C26, C2710 pFWalsin0402N100J500CTCAP, CERM, 10 pF, 50 V,
+/- 5%, C0G/NP0, 0402
2C28, C306.2 pFWalsin0402N6R2C500CTCAP, CERM, 6.2 pF, 50 V,
+/- 4%, C0G/NP0, 0402
3J1, J2, J3Wurth Elektronik61300311121Header, 2.54 mm, 3x1, Gold, TH
2L1, L32.2 µHMuRataLQM2MPN2R2NG0Inductor, Multilayer, Ferrite,
2.2 uH, 1.2 A, 0.11 ohm, SMD
1L21 µHMuRataLQM2HPN1R0MG0LInductor, Multilayer, Ferrite,
1 uH, 1.6 A, 0.055 ohm, SMD
1L4(1)10 µHTDKMLP2520S100MT0S1Inductor, Multilayer, Ferrite,
10 uH, 0.7 A, 0.364 ohm, SMD
5R1, R2, R3, R4, R9100kVishay-DaleCRCW0402100KJNEDRES, 100 k, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
1R5(2)0PanasonicERJ-2GE0R00XRES, 0, 5%, 0.063 W, 0402
1R6270Vishay-DaleCRCW0402270RJNEDRES, 270, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
4R7, R8, R10, R1169.8kVishay-DaleCRCW040269K8FKEDRES, 69.8 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
1U1Macronix International Co., LTDMX25R3235FM1IL0Ultra low power, 32M-bit
[x 1/x 2/x 4] CMOS MXSMIO(serial multi I/O) Flash memory, SOP-8
1U2Texas InstrumentsCC3235SF12RGKRSimpleLink Wi-Fi and Internet-of-Things Solution, a Single-Chip Wireless MCU, RGK0064B (VQFN-64)
1Y1Abracon CorporationABS07-32.768KHZ-9-TCrystal, 32.768KHz, 9PF, SMD
1Y2TXC Corporation8Y40072002Crystal, 40 MHz, 8 pF, SMD
(1) For the CC3235SF device, L4 is populated. For the CC3235S device, L4 is not populated.
(2) For the CC3220SF device, R5 is not populated. For the CC3235S device if R5 is populated, Pin 45 can be used as GPIO_31.
CC3235S CC3235SF CC3235x RF Schematic Implementation with and without CoexistenceFigure 9-8 CC3235x RF Schematic Implementation with and without Coexistence

 

Note:

The Following guidelines are recommended for implementation of the RF design:

  • Ensure an RF path is designed with an impedance of 50Ω.
  • Tuning of the antenna impedance π matching network is recommended after manufacturing of the PCB to account for PCB parasitics.
  • π or L matching and tuning may be required between cascaded passive components on the RF path.
Table 9-2 Bill of Materials For CC3235x RF Section
QuantityDesignatorValueManufacturerPart NumberDescription
3C31(1), C32(1), C33(1)68 pFMurataGRM0335C1H680JA1DCAP, CERM, 68 pF, 50 V,
+/- 5%, C0G/NP0, 0201
4C34(1), C35(1), C42, C43100 pFYageoCC0201JRNPO8BN101CAP, CERM, 100 pF, 25 V,
+/- 5%, C0G/NP0, 0201
1C368.2 pFWalsin0402N8R2C500CTCAP, CERM, 8.2 pF, 50 V,
+/- 3%, C0G/NP0, 0402
1C372.2 pFMuRataGJM1555C1H2R2BB01DCAP, CERM, 2.2 pF, 50 V,
+/- 4.5%, C0G/NP0, 0402
1C381.6 pFMuRataGRM0335C1H1R6BA01DCAP, CERM, 1.6 pF, 50 V,
+/- 7%, C0G/NP0, 0201
1C391.9 pFMuRataGJM1555C1H1R9WB01DCAP, CERM, 1.9 pF, 50 V,
+/- 2.6%, C0G/NP0, 0402
2C40, C414.7 pFMuRataGRM0335C1H4R7BA01DCAP, CERM, 4.7 pF, 50 V,
+/- 3%, C0G/NP0, 0201
1E1EthertronicsM830520WLAN Antenna 802.11, SMD
1FL1TDKDEA202450BT-1294C1-HMultilayer Chip Band Pass Filter For 2.4 GHz W-LAN/Bluetooth, SMD
1FL2TDKDEA165538BT-2236B1-HMultilayer Band Pass Filter For
5 GHz W-LAN/LTE-U
1L53.9 nHMuRataLQG15HS3N9S02DInductor, Multilayer, Air Core,
3.9 nH, 0.75 A, 0.14 ohm, SMD
1L62.7 nHMuRataLQG15WH2N7C02DInductor, Multilayer, Air Core,
2.7 nH, 0.9 A, 0.07 ohm,
AEC-Q200 Grade 1, SMD
2R12(1), R13(1)100kVishay-DaleCRCW0402100KJNEDRES, 100 k, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
2U3(1), U5RichwaveRTC6608OSP0.03 GHz-6 GHz SPDT Switch
1U4TDKDPX165950DT-8148A1Multilayer Diplexer for 2.4 GHz W-LAN & Bluetooth / 5 GHz
W-LAN
(1) If the BLE/2.4GHz coexistence features is not used, these components are not required.