JAJSH80C august   1998  – march 2023 CD4051B-Q1 , CD4053B-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - CD4051B-Q1
    6. 6.6 AC Performance Characteristics - CD4051B-Q1
    7. 6.7 Electrical Characteristics - CD4053B-Q1
    8. 6.8 AC Performance Characteristics - CD4053B-Q1
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-1F2659C4-F1EF-4143-987B-F0D9D1D407BC-low.svgFigure 5-1 CD4051B-Q1D or PW Package,(Top View)
Table 5-1 Pin Functions CD4051B-Q1
PIN TYPE(1) DESCRIPTION
NO. NAME
1 CH 4 IN/OUT I/O Channel 4 in/out
2 CH 6 IN/OUT I/O Channel 6 in/out
3 COM OUT/IN I/O Common out/in
4 CH 7 IN/OUT I/O Channel 7 in/out
5 CH 5 IN/OUT I/O Channel 5 in/out
6 INH I Disables all channels. See Table 8-1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 8-1.
10 B I Channel select B. See Table 8-1.
11 A I Channel select A. See Table 8-1.
12 CH 3 IN/OUT I/O Channel 3 in/out
13 CH 0 IN/OUT I/O Channel 0 in/out
14 CH 1 IN/OUT I/O Channel 1 in/out
15 CH 2 IN/OUT I/O Channel 2 in/out
16 VDD — Positive power input
(1) I = input, O = output
GUID-4165EFBA-D1D5-42A2-9E9F-3894261C44B7-low.svg Figure 5-2 CD4053B-Q1D or PW Package,(Top View)
Table 5-2 Pin Functions CD4053B-Q1
PIN TYPE(1) DESCRIPTION
NO. NAME
1 BY IN/OUT I/O B channel Y in/out
2 BX IN/OUT I/O B channel X in/out
3 CY IN/OUT I/O C channel Y in/out
4 CX OR CY OUT/IN I/O C common out/in
5 CX IN/OUT I/O C channel X in/out
6 INH I Disables all channels. See Table 8-1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 8-1.
10 B I Channel select B. See Table 8-1.
11 A I Channel select A. See Table 8-1.
12 AX IN/OUT I/O A channel X in/out
13 AY IN/OUT I/O A channel Y in/out
14 AX OR AY OUT/IN I/O A common out/in
15 BX OR BY OUT/IN I/O B common out/in
16 VDD — Positive power input
(1) I = input, O = output