In applications where separate power sources are used to drive V_DD and the signal inputs, the V_DD current capability should exceed V_DD/R_L (R_L = effective external load). This provision avoids permanent current flow or clamp action on the V_DD supply when power is applied or removed from the CD40x7B.

When switching from one address to another, some of the ON periods of the channels of the multiplexers will overlap momentarily, which may be objectionable in certain applications. Also, when a channel is turned on or off by an address input, there is a momentary conductive path from the channel to V_SS, which will dump some charge from any capacitor connected to the input or output of the channel. the inhibit input turning on a channel will similarly dump some charge to V_SS.

The amount of charge dumped is mostly a function of the signal lave above V_SS. Typically, at V_DD–V_SS = 10V, a 100pF capacitor connected to the input or output of the channel will lose 3-4% of its voltage at the moment the channel turns on or off. This loss of voltage is essentially independent of the address or inhibit signal transition time, if the transition time is less than 1-2µs. When the inhibit signal turns a channel off, there is no charge dumping to V_SS. Rather, there is a slight rise in the channel voltage level (65mV typical) due to capacitive coupling from inhibit input to channel input or output. Address inputs also couple some voltage steps onto the channel signal levels.

In certain applications, the external load-resistor current may include both V_DD and signal-line components. To avoid drawing V_DD current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.8V (calculated from RTON values shown in Electrical Characteristics tables). No V_DD current will flow through R_L if the switch current flows into terminal 1 on the CD4067B, terminals 1 and 17 on the CD4097B.