JAJSV57A December   2002  – July 2024 CD54ACT74 , CD74ACT74

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • J|14
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

CD54ACT74 CD74ACT74 D, N, or J Package14-Pin SOIC, PDIP, or CDIP(Top View) Figure 3-1 D, N, or J Package
14-Pin SOIC, PDIP, or CDIP
(Top View)
Table 3-1 Pin Functions
PIN TYPE1 DESCRIPTION
NAME NO.
1CLR 1 I Asynchronous clear for channel 1, active low
1D 2 I Data for channel 1
1CLK 3 I Clock for channel 1, rising edge triggered
1PRE 4 I Asynchronous preset for channel 1, active low
1Q 5 O Output for channel 1
1Q 6 O Inverted output for channel 1
GND 7 G Ground
2Q 8 O Inverted output for channel 2
2Q 9 O Output for channel 2
2PRE 10 I Asynchronous preset for channel 2, active low
2CLK 11 I Clock for channel 2, rising edge triggered
2D 12 I Data for channel 2
2CLR 13 I Asynchronous clear for channel 2, active low
VCC 14 P Positive supply
  1. Signal Types: I = Input, O = Output, I/O = Input or Output.