6 Parameter Measurement Information

t_PD is the maximum between t_PLH and t_PHL

t_t is the maximum between t_TLH and t_THL

NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in accordance with device truth table. For f_MAX, input duty cycle = 50%

Figure 6-1 HC clock pulse rise and fall times and pulse width

Figure 6-3 HC and HCU transition times and propagation delay times, combination logic

Figure 6-5 HC setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits

Figure 6-7 HC three-state propagation delay waveform

NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in accordance with device truth table. FOr f_MAX, input duty cycle = 50%

Figure 6-2 HCT clock pulse rise and fall times and pulse width

Figure 6-4 HCT transition times and propagation delay times, combination logic

Figure 6-6 HCT setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits

Figure 6-8 HCT three-state propagation delay waveform

NOTE: Opend drain waveforms t_PLZ and t_PZL are the same as those for three-state shown on the left. The test circuit is Output R_L = 1kΩ to V_CC, C_L = 50pF

Figure 6-9 HC and HCT three-state propagation delay test circuit