JAJSND6D November   1997  – November 2021 CD54HC259 , CD54HCT259 , CD74HC259 , CD74HCT259

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics (2)
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

7.3 Device Functional Modes

The Function Tableand Latch Selection Table below list the functional modes of the CDx4HC(T)259.

Table 7-1 Function Table
INPUTS(1) OUTPUT OF ADDRESSED LATCH(2) EACH OTHER OUTPUT(2) FUNCTION
CLR G
H L D QiO Addressable latch
H H QiO QiO Memory
L L D L 8-line demultiplexer
L H L L Clear
(1) H = High voltage level, L = Low voltage level
(2) QiO = Previous output state of selected latch, D = Data input logic value
Table 7-2 Latch Selection Table
SELECT INPUTS(1) LATCH ADDRESSED
S2 S1 S0
L L L 0
L L H 1
L H L 2
L H H 3
H L L 4
H L H 5
H H L 6
H H H 7
(1) H = High Voltage Level, L = Low Voltage Level