JAJSO95F September   1997  – March 2022 CD54HC393 , CD54HCT393 , CD74HC393 , CD74HCT393

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

5.6 Switching Characteristics

Input tr, tf = 6 ns. See (Parameter Measurement Information)
PARAMETER TEST CONDITIONS VCC (V) 25℃ -40℃ to 85℃ -55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL

Propagation delay time

nCP to nQ0

 CL = 50 pF 2 150 190 225 ns
4.5 30 38 59
CL = 15 pF 5 12 ns
CL = 50 pF 6 26 33 50 ns
tPLH, tPHL nCP to nQ1 CL = 50 pF 2 190 245 295 ns
4.5 38 49 59
6 33 42 50
tPLH, tPHL nCP to nQ2 CL = 50 pF 2 240 300 360 ns
4.5 48 60 72
6 41 51 61
tPLH, tPHL nCP to nQ3 CL = 50 pF 2 285 355 430 ns
4.5 57 71 86
6 48 60 73
tPLH, tPHL MR to Qn CL = 50 pF 2 135 170 205 ns
4.5 27 34 41
CL = 15 pF 5 11 ns
CL = 50 pF 6 23 29 35
tTLH, tTHL Output transition time CL = 50 pF 2 75 95 110 ns
4.5 15 19 22
6 13 16 19
CIN Input capacitance CL = 50 pF 10 10 10 pF
CPD Power dissipation capacitance(1)(2) CL = 15 pF 5 20 pF
HCT TYPES
tPLH, tPHL

Propagation delay time

nCP to nQ0

 CL = 50 pF 4.5 32 40 48 ns
CL = 15 pF 5 13 ns
tPLH, tPHL nCP to nQ1 CL = 50 pF 4.5 44 55 66 ns
tPLH, tPHL nCP to nQ2 CL = 50 pF 4.5 50 63 75 ns
tPLH, tPHL nCP to nQ3 CL = 50 pF 4.5 62 78 93 ns
tPLH, tPHL MR to Qn CL = 50 pF 4.5 32 40 48 ns
CL = 15 pF 5 13 ns
tTLH, tTHL Output transition CL = 50 pF 4.5 15 19 22 ns
CIN Input capacitance CL = 15 pF 10 10 10 pF
CPD Power dissipation capacitance(1)(2) CL = 15 pF 5 21 pF
(1) CPD is used to determine the dynamic power consumption, per stage.
(2) PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.