JAJSHG0N November   1997  – April 2024 CD54HC4051 , CD54HC4052 , CD54HC4053 , CD54HCT4051 , CD74HC4051 , CD74HC4052 , CD74HC4053 , CD74HCT4051 , CD74HCT4052 , CD74HCT4053

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics: HC Devices
    6. 5.6  Electrical Characteristics: HCT Devices
    7. 5.7  Switching Characteristics, VCC = 5V
    8. 5.8  Switching Characteristics, CL = 50pF
    9. 5.9  Analog Channel Specifications
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

4 Pin Configuration and Functions

GUID-207BCFD1-F213-492B-910A-DDB2EEC734B2-low.gifFigure 4-1 CDx4HCx4051 J, N, D, NS, PW Packages 16-Pin CDIP, PDIP, SOIC, SO, TSSOP (Top View)
Table 4-1 Pin Functions for CDxHCx4051B

PIN

 TYPE(1)

DESCRIPTION

NAME

NO.

CH A4 IN/OUT

1

 I/O

Channel 4 in/out

CH A6 IN/OUT

2

 I/O Channel 6 in/out

COM OUT/IN

3

 I/O

Common out/in

CH A7 IN/OUT

4

 I/O Channel 7 in/out

CH A5 IN/OUT

5

 I/O Channel 5 in/out

!E

6

 I

Enable Channels (Active Low)

VEE

7

 —

Negative power input

GND

8

 —

Ground

S2

9

 I

Channel select 2

S1

10

 I

Channel select 1

S0

11

 I

Channel select 0

CH A3 IN/OUT

12

 I/O Channel 3 in/out

CH A0 IN/OUT

13

 I/O Channel 0 in/out

CH A1 IN/OUT

14

 I/O Channel 1 in/out

CH A2 IN/OUT

15

I/O

 Channel 2 in/out

VCC

16

 —

Positive power input
(1) I = input, O = output
GUID-60358B2B-7DA9-4CE7-88D6-1E42F072593F-low.gif Figure 4-2 CDx4HCx4052 J, N, D, NS, PW Packages 16-Pin CDIP, PDIP, SOIC, SO, TSSOP (Top View)
Table 4-2 Pin Functions for CDx4HCx4052B

PIN

 TYPE(1)

DESCRIPTION

NAME

NO.

CH B0 IN/OUT

1

I/O

Channel B0 in/out

CH B2 IN/OUT

2

 I/O

Channel B2 in/out

COM B OUT/IN

3

 I/O

B common out/in

CH B3 IN/OUT

4

 I/O

Channel B3 in/out

CH B1 IN/OUT

5

 I/O

Channel B1 in/out

!E

6

 I

Enable channels (Active Low)

VEE

7

 —

Negative power input

GND

8

 —

Ground

S1

9

 I

Channel select 1

S0

10

 I

Channel select 0

CH A3 IN/OUT

11

 I/O

Channel A3 in/out

CH A0 IN/OUT

12

 I/O

Channel A0 in/out

COM A IN/OUT

13

 I/O

A common out/in

CH A1 IN/OUT

14

 I/O

Channel A1 in/out

CH A2 IN/OUT

15

 I/O

Channel A2 in/out

VCC

16

 —

Positive power input
(1) I = input, O = output
GUID-E66ECE2E-E34C-404A-A502-A59F5F4F6C38-low.gif Figure 4-3 CDx4HCx4053 J, N, D, NS, PW Packages 16-Pin CDIP, PDIP, SOIC, SO, TSSOP (Top View)
Table 4-3 Pin Functions CDx4HCx4053B

PIN

 TYPE(1)

DESCRIPTION

NAME

NO.

B1IN/OUT

1

I/O

B channel Y in/out

B0 IN/OUT

2

I/O

B channel X in/out

C1 IN/OUT

3

I/O

C channel Y in/out

COM C OUT/IN

4

I/O

C common out/in

C0 IN/OUT

5

I/O

C channel X in/out

!E

6

I

Enable channels (Active Low)

VEE

7

 —

Negative power input

GND

8

 —

Ground

S2

9

I

Channel select 2

S1

10

I

Channel select 1

S0

11

I

Channel select 0

A0 IN/OUT

12

I/O

A channel X in/out

A1 IN/OUT

13

I/O

A channel Y in/out

COM A OUT/IN

14

I/O

A common out/in

COM B OUT/IN

15

I/O

B common out/in

VCC

16

 —

Positive power input
(1) I = input, O = output