JAJSNM9 データシート

JAJSNM9C February 1998 – December 2021 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

J|20

サーマルパッド・メカニカル・データ

発注情報

5.4 Electrical Characteristics

PARAMETER		TEST CONDITIONS^⁽²⁾	V_CC (V)	25℃			–40℃ to 85℃		–55℃ to 125℃		UNIT
PARAMETER		TEST CONDITIONS^⁽²⁾	V_CC (V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNIT
HC TYPES
V_IH	High level input voltage		2	1.5			1.5		1.5		V
			4.5	3.15			3.15		3.15
			6	4.2			4.2		4.2
V_IL	Low level input voltage		2			0.5		0.5		0.5	V
			4.5			1.35		1.35		1.35
			6			1.8		1.8		1.8
V_OH	High level output voltage CMOS loads	I_OH = – 20 μA	2	1.9			1.9		1.9		V
		I_OH = – 20 μA	4.5	4.4			4.4		4.4
		I_OH = – 20 μA	6	5.9			5.9		5.9
	High level output voltage TTL loads	I_OH = – 4 mA	4.5	3.98			3.84		3.7		V
	High level output voltage TTL loads	I_OH = – 5.2 mA	6	5.48			5.34		5.2		V
V_OL	Low level output voltage CMOS loads	I_OL = 20 μA	2			0.1		0.1		0.1	V
		I_OL = 20 μA	4.5			0.1	-	0.1	-	0.1
		I_OL = 20 μA	6			0.1		0.1		0.1
	Low level output voltage TTL loads	I_OL = 4 mA	4.5			0.26		0.33		0.4	V
	Low level output voltage TTL loads	I_OL = 5.2 mA	6			0.26		0.33		0.4	V
I_I	Input leakage current	V_I = V_CC or GND	6			±0.1		±1		±1	mA
I_CC	Quiescent device current	V_I = V_CC or GND	6			8		80		160	mA
HCT TYPES
V_IH	High level input voltage		4.5 to 5.5	2			2		2		V
V_IL	Low level input voltage		4.5 to 5.5			0.8		0.8		0.8	V
V_OH	High level output voltage CMOS loads	I_OH = – 20 μA	4.5	4.4			4.4		4.4		V
V_OH	High level output voltage TTL loads	I_OH = – 4 mA	4.5	3.98			3.84		3.7		V
V_OL	Low level output voltage CMOS loads	I_OL = 20 μA	4.5			0.1		0.1		0.1	V
V_OL	Low level output voltage TTL loads	I_OL = 4 mA	4.5			0.26		0.33		0.4	V
I_I	Input leakage current	V_I = V_CC or GND	5.5			±0.1		±1		±1	μA
I_CC	Quiescent device current	V_I = V_CC or GND	5.5			8		80		160	μA
ΔI_CC⁽¹⁾	Additional quiescent device current per input pin	CLR input held at V_CC –2.1	4.5 to 5.5		100	540		675		735	μA
		Data inputs held at V_CC –2.1	4.5 to 5.5		100	144		180		196	μA
		CLK inputs held at V_CC –2.1	4.5 to 5.5		100	540		675		735	μA

(1) For dual-supply systems theoretical worst case (V_I = 2.4 V, V_CC = 5.5 V) specification is 1.8mA.

(2) V_I = V_IH or V_IL, unless otherwise noted.