JAJSOX8C November   1998  – July 2022 CD54HC640 , CD54HCT640 , CD74HC640 , CD74HCT640

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics (2)
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • J|20
サーマルパッド・メカニカル・データ
発注情報

5.5 Switching Characteristics(2)

Input tt = 6ns. Unless otherwise specified, CL = 50pF
PARAMETER VCC (V) 25°C -40°C to 85°C -55°C to 125°C UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tpd Propagation delay
A to B
B to A		 2 90 115 135 ns
4.5 7(1) 18 23 27
6 15 20 23
tpd Propagation delay
Output High-Z
To high level,
low level		 2 150 190 225 ns
4.5 12(1) 30 38 45
6 26 33 38
tpd Propagation delay
Output high level
Output lowe level to high Z		 2 150 190 225 ns
4.5 12(1) 30 38 45
6 26 33 38
tt Output transition time 2 60 75 90 ns
4.5 12 15 18
6 10 13 15
Ci Input Capacitance 10 10 10 10 pF
CO Three-state output capacitance 20 20 20 pF
Cpd Power dissipation capacitance (3)(4) 5 38 pF
HCT TYPES
tpd Propagation delay
A to B
B to A		 4.5 9(1) 22 28 33 ns
tpd Propagation delay
Output High-Z
To high level,
low level		 4.5 12(1) 30 38 ns
tpd Propagation delay
Output high level
Output lowe level to high Z		 4.5 12(1) 30 38 ns
tt Transition times 4.5 12 15 ns
Ci Input capacitance 10 10 10 pF
CO Three-state output capacitance 20 20 pF
Cpd Power dissipation capacitance (3)(4) 5 41 pF
(1) Typical value tested at 5V, CL = 15pF.
(2) For details on CMOS power calculation see, SCAA053B
(3) CPD is used to determine the dynamic power consumption, per channel
(4) PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.