JAJSO09F August   1997  – February 2022 CD54HC4002 , CD74HC4002

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • PW|14
  • N|14
サーマルパッド・メカニカル・データ
発注情報

5.5 Switching Characteristics

Input tr, tf = 6 ns
PARAMETER TEST CONDITIONS VCC (V) 25℃ -40℃ to 85℃ -55℃ to 125℃ UNIT
TYP MAX MAX MAX
HC TYPES
tPLH, tPHL Propagation delay,

nA, nB, nC, nD to nY

 CL = 50 pF 2 100 125 150 ns
4.5 20 25 30 ns
6 17 21 26 ns
CL = 15 pF 5 8 ns
tTLH, tTHL Output transition times (see Figure 1) CL = 50 pF 2 75 95 110 ns
4.5 15 19 22 ns
6 13 16 19 ns
CIN Input capacitance 10 10 10 pF
CPD Power dissipation capacitance(1)(2) CL = 15 pF 5 22 pF
(1) CPD is used to determine the dynamic power consumption, per gate.
(2) PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.