JAJSMC7 June 2020 CD54HCT20 , CD74HCT20
PRODUCTION DATA
TTL-Compatible CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-73C3CD82-C52A-4B0F-A527-6CBE4EFFAF31.html#GUID-73C3CD82-C52A-4B0F-A527-6CBE4EFFAF31. The worst case resistance is calculated with the maximum input voltage, given in the GUID-172FD3DA-F0B2-4490-8CC7-F049321F0FD7.html#GUID-172FD3DA-F0B2-4490-8CC7-F049321F0FD7, and the maximum input leakage current, given in the GUID-73C3CD82-C52A-4B0F-A527-6CBE4EFFAF31.html#GUID-73C3CD82-C52A-4B0F-A527-6CBE4EFFAF31, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the GUID-053D1AA2-AD86-4113-ABB3-6E4ECEA601E2.html#GUID-053D1AA2-AD86-4113-ABB3-6E4ECEA601E2 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the TTL-compatible CMOS input.
TTL-Compatible CMOS inputs have a lower threshold voltage than standard CMOS inputs to allow for compatibility with older bipolar logic devices. See the GUID-053D1AA2-AD86-4113-ABB3-6E4ECEA601E2.html#GUID-053D1AA2-AD86-4113-ABB3-6E4ECEA601E2 for the valid input voltages for the CD74HCT20.