JAJSKP6A August   2021  – May 2022 CDCDB803

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input
      2. 8.3.2 Output Enable Control
      3. 8.3.3 SMBus
        1. 8.3.3.1 SMBus Address Assignment
    4. 8.4 Device Functional Modes
      1. 8.4.1 CKPWRGD_PD# Function
      2. 8.4.2 OE[7:0]# and SMBus Output Enables
      3. 8.4.3 Output Slew Rate Control
      4. 8.4.4 Output Impedance Control
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CDCDB803 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Enable Control Method
        2. 9.2.2.2 SMBus Address
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TICS Pro
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_A = 3.3 V, 25°C (unless otherwise noted)
MIN NOM MAX UNIT
SMBUS-COMPATIBLE INTERFACE TIMING
fSMB SMBus operating frequency 10 400 kHz
tBUF Bus free time between STOP and START 4.7 µs
tHD_STA START condition hold time SMBCLK low after SMBDAT low 4
tSU_STA START condition setup time SMBCLK high before SMBDAT low 4.7
tSU_STO STOP condition setup time 4
tHD_DAT SMBDAT hold time 300 ns
tSU_DAT SMBDAT setup time 250
tTIMEOUT Detect SMBCLK low timeout In terms of device input clock frequency 1e6 cycles
tLOW SMBCLK low period 4.7 µs
tHIGH SMBCLK high period 4 50
tF SMBCLK/SMBDAT fall time(1) 300 ns
tR SMBCLK/SMBDAT rise time(2) 1000
(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)
(2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15)