DATA SHEET
CDCE62002 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
1 Features
- Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter
- Fully Configurable Outputs Including Frequency and Output Format
- Smart Input Multiplexer Automatically Switches Between One of Two Reference Inputs
- Multiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover Mode
- Integrated EEPROM Determines Device Configuration at Power Up
- Excellent Jitter Performance
- Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:
- Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode
- Programmable Charge Pump Gain and Loop Filter Settings
- Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.
- Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:
- 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
- Low Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHz
- Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode
- LVPECL, LVDS, and LVCMOS
- Independent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32
- Flexible Inputs With Innovative Smart Multiplexer:
- Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)
- One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHz
- Clock Generator Mode Using Crystal Input
- Smart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe Operation
- Typical Power Consumption 750 mW at 3.3 V
- Integrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined State
- Offered in QFN-32 Package
- ESD Protection Exceeds 2000 V HBM
- Industrial Temperature Range: –40°C to +85°C
2 Applications
- Data Converter and Data Aggregation Clocking
- Wireless Infrastructure
- Switches and Routers
- Medical Electronics
- Military and Aerospace
- Industrial
- Clock Generation and Jitter Cleaning
3 Description
The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS (1).
(1)10-kHz to 20-MHz integration bandwidth.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| CDCE62002 | VQFN (32) | 5.00 mm × 5.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
CDCE62002 Application Example
4 Revision History
Changes from D Revision (February 2012) to E Revision
- Added figure cross references to Electrical TablesGo
- Added figure titles.Go
- Updated Figure 18Go
- Updated Figure 20Go
- Corrected description for bits 0 and 1 in CDCE62002 Register 0 Bit Definitions Go
- Corrected the register bits for LVPECL-AC, LVPECL-DC, LVDS-AC, LVDS-DC reference inputs in Reference Input AC/DC Input Termination Table Go
Changes from C Revision (March 2011) to D Revision
- Added 3 rows in TIMING REQUIREMENTS table, under Duty Cycle rowGo
- Added a sentence below Equation 3Go
- Changed last row last column in Figure 23 truth table from Disabled to Input Buffer Termination DisabledGo
- Changed in Table 13, second column, 5th and 6th row from 1 to 0Go
- Added a reference to Table 11 and 2 references to Table 12 in Table 6Go
- Added 6 crossreferences to Table 8 Go
- Changed changed last row in Table 8 Description column, from "always reads 1" to "May read back to 1 or 0"Go
Changes from B Revision (February 2010) to C Revision
- Changed the description of Pin 30, REF_IN-.Go
- Changed Pin 7 to open drain in Pin Functions tableGo
- Changed the description of Pin 19, TESTSYNC To: Reserved Pin.....resistor.Go
- Changed pin 31 From: Power To: A. Power in Pin Functions tableGo
- Changed Pin Functions table, Pins 9, 12 to VCC_OUT0. Pins 13 and 16 to VCC_OUT1Go
- Changed Note1 of the Pin Functions tableGo
- Deleted Dividers and from ELEC CHARACTERISTICS table in row POFFGo
- Changed Crytal input section first row From: Crystal Load Capacitance To: On-chip Load CapacitanceGo
- Added SPI OUTPUT row From: PLL To: PLL_LOCKGo
- Changed tr / tf Max value From: 735 To: 135Go
- Deleted (Reg 0 RAM bit 9 = 1) and (Reg 0 RAM bit 9 = 0) from the TIMING REQUIREMENTS table Go
- Added Driver Level and Max shunt capacitance to AUXILARY_IN REQUIREMENT in the TIMING REQUIREMENTS tableGo
- Deleted Columns from Table 1: LVDS-HP and LVCMOS-HPGo
- Changed Table 2 Go
- Changed the OUTPUT TO OUTPUT ISOLATION sectionGo
- Deleted the SPI CONTROL INTERFACE TIMING sectionGo
- Updated Figure 18Go
- Updated Reference Input Buffer Go
- Updated Figure 20Go
- Changed the Smart Multiplexer Dividers sectionGo
- Changed Changed the text in the Smart Multiplexer Divider sectionGo
- Changed Figure 24Go
- Deleted column 3 db Corner C3R3 from Table 12Go
- Added sections: VCO Calibration, Crystal Input Interface, and Startup TimeGo
- Changed Figure 29Go
- Changed the INTERFACE AND CONTROL BLOCK sectionGo
- Changed figure Figure 36Go
- Changed Table 17, RAM BITS To REGISTER BITSGo
- Deleted the First four rows in Table 18 and the first columnGo
- Deleted (6 settings+DisAble+Enable) in Register bit 19 of Table 18Go
- Added ; set '0' to TI use Only in bit 26 in Table 18Go
- Changed the description of bit 27 in Table 18Go
- Deleted the First four rows in Table 19 and the first columnGo
- Added Receiving Notification of Documentation Updates section Go
Changes from A Revision (July, 2009) to B Revision
- Deleted feature reference to Single Ended Clock Source or Crystal and LVCMOS Input of up to 75 MHz Go
- Deleted references to single ended inputs and CMOS clock from description.Go
- Changed the description of Pin 2, AUX_INGo
- Deleted LVCMOS INPUT MODE (AUX_IN) section from Electrical CharacteristicsGo
- Changed Crystal Shunt Capacitance to Crystal Load Capacitance with a MIN value of 8Go
- Deleted fREF – Single paramter from AUXILARY_IN_REQUIRMENTSGo
- Deleted references to EEPROM Locking from "Interface and Control Block" sectionGo
- Changed Auxiliary Input Port sectionGo
- Deleted External Feed Back Mode sectionGo
- Deleted External Feedback Option sectionGo
- Changed EXTFEEDBACK to RESERVED for bit 10 in Table 16Go
- Changed EELOCK to RESERVED for bit 30 in Table 18Go
Changes from * Revision (June 2009) to A Revision
- Added information to Pin 18 description - The input has an internal 150-kΩ pull-up resistGo
- Added NOTE: All VCC pins need to be connected for the device to operate properly.Go
- Changed PLVPECL, PLVDS, PLVCMOS and POFF Unit values From: W To: mWGo
- Deleted underscore before IN+Go
- Deleted 6 from 8006Go
- Changed Y4 to Y1Go
- Added tr / tf MIN, TYP, and MAX valuesGo
- Added (Reg 0 RAM bit 9 = 0) to fREF – Diff REF_DIV Go
- Changed graphic input namingGo
- Changed graphic input namingGo
- Changed REF into REF_INGo
- Changed graphicGo
- Changed Table 4Go
- Changed PDDRESET to PLLRESET, in Table 4Go
- Changed Power_Down to PD, in Table 4Go
- Changed PRI_IN to REF_IN in Figure 19Go
- Changed PRI_IN to REF_INGo
- Changed PRI_IN to REF_INGo
- Changed part number errorGo
- Changed REFERENCE to REF_IN and AUXILARY to AUX_IN, Table 16Go
- Changed power to currentGo
- Changed the description of bits 0 - 5 To: TI Test Registers. For TI Use Only in Table 19Go
5 Description (continued)
It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz (1)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
(1)Frequency range depends on operational mode and output format selected.
6 Pin Configuration and Functions
RHB Package
32-Pin QFN
Top View
Pin Functions
| PIN | TYPE | DESCRIPTION(1) | |
|---|---|---|---|
| NAME | NO. | ||
| AUX_IN | 2 | I | Auxiliary Input is a Crystal input pin that connect to an internal oscillator circuitry. |
| EXT_LFN | 26 | Analog | External Loop Filter Input Negative. |
| EXT_LFP | 25 | Analog | External Loop Filter Input Positive |
| GND | PAD | Ground | Ground is on Thermal PAD. See Layout Guidelines |
| GND_PLLDIV | 21 | Ground | Ground for PLL Divider circuitry. (short to GND) |
| PD | 6 | I | PD or Power-Down Pin is an active low pin and can be activated externally or through the corresponding Bit in SPI Register 2 While PD is asserted (low), the device is shut down. When PD switches high the EEPROM becomes loaded into the RAM. After the selected input clock signal becomes available, the VCO starts calibration and the PLL aims to achieve lock. All Output dividers become initiated. During self-calibration, the outputs are held static (for example, logical zero). PD pin has an internal 150-kΩ pullup resistor. Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAM on the Rising edge of PD. |
| PLL_LOCK | 32 | O | PLL Lock indicator |
| REF_IN+ | 29 | I | Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Reference Clock. |
| REF_IN– | 30 | I | Universal Input Buffer (LVPECL, LVDS,) negative input for the Reference Clock. This pin must be pulled to ground through 1-kΩ resistor when input is selected LVCMOS. |
| REG_CAP1 | 5 | Analog | Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V) |
| REG_CAP2 | 27 | Analog | Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V) |
| REG_CAP3 | 20 | Analog | Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V) |
| REG_CAP4 | 23 | Analog | Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V) |
| SPI_CLK | 17 | I | LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. |
| SPI_LE | 18 | I | LVCMOS input, control Latch Enable for Serial Programmable Interface. Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly on the Rising edge of PD. The input has an internal 150-kΩ pull-up resistor |
| SPI_MISO | 7 | O | 3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data Output to the SPI bus interface. |
| SPI_MOSI | 8 | I | LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62002 for the SPI bus interface. |
| TESTSYNC | 19 | I | Reserved Pin. Pull this pin down to ground using 1-kΩ resistor. |
| U0P:U0N U1P:U1N |
11,10 15,14 |
O | The outputs of CDCE62002 are user definable and can be any combination of up to 2 LVPECL outputs, 2 LVDS outputs or up to 4 LVCMOS outputs. The outputs are selectable through SPI interface. The power-up setting is EEPROM configurable. |
| VBB | 3 | Analog | Capacitor for the internal termination Voltage. Connect to a 1-μF Capacitor (Y5V) |
| VCC_AUX | 1 | A. Power | 3.3-V Supply Power for Crystal/Auxiliary Input Buffer Circuitry |
| VCC_IN | 31 | A. Power | 3.3-V Supply Power for Input Buffer Circuitry |
| VCC_OUT0 | 9, 12 | Power | 3.3-V Supply for the Output Buffers. |
| VCC_OUT1 | 13, 16 | ||
| VCC_PLLA | 28 | A. Power | 3.3-V Supply Power for the PLL circuitry. |
| VCC_PLLD | 4 | Power | 3.3-V Supply Power for the PLL circuitry. |
| VCC_PLLDIV | 22 | Power | 3.3-V Supply Power for the PLL circuitry. |
| VCC_VCO | 24 | A. Power | 3.3-V Supply Power for the VCO circuitry. |
(1) It is furthermore recommended to use a supply filter for each VCC supply domain independently. A minimum requirement is to group the supplies into four independent groups:
VCC_PLLA + VCC_VCO
VCC_PLLD + VCC_PLLDIV
VCC_IN + VCC_AUXIN
VCC_OUT0 + VCC_OUT1
All VCC pins need to be connected for the device to operate properly.
VCC_PLLA + VCC_VCO
VCC_PLLD + VCC_PLLDIV
VCC_IN + VCC_AUXIN
VCC_OUT0 + VCC_OUT1
All VCC pins need to be connected for the device to operate properly.
