The device digital logic starts after the internal power-on-release circuit triggered (POR). The digital core is connected to the VDDREF domain. The EEPROM settings are loaded into the device registers and the new settings applied to the device. The EEPROM page is selected according to the EEPROMSEL pin logic level. A low level loads page 0, and a logic high level loads page 1. By default, the differential outputs are muted for the initial VCO calibration and PLL lock process. After the PLL circuit achieved a phase lock to the input reference, the output dividers are synchronized and then released to operation. By default, pin 8 is configured as RESETN pin (see gpio0_dir_sel and gpio0_input_sel). The start of the initialization sequence, as well the as serial interface, can be kept in reset using RESETN= LOW. When pin 8 is not configured as RESETN, the device initialization relies on the POR triggered by application of VDDREF.

Figure 9-5 Initialization Flow Chart

The pins 8, 11, 12, 19, and 20 are general-purpose inputs and outputs (GPIO). The functions are determined through the register settings saved in the selected EEPROM page. See Generic0, Generic1, and Ceneric2for the relevant bit-fields.

The EEPROM allows to choose between two modes of operation: pin Mode and serial interface mode. This is done using mode.