JAJSDY3 データシート | TI.com

JAJSDY3F July 2017 – January 2024 CDCI6214

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RGE|24

サーマルパッド・メカニカル・データ

発注情報

6.15 HCSL Output Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A = –40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_{O_HCSL}	Output frequency		0.1		350	MHz
V_{CM_HCSL}	Output common mode		0.2	0.34	0.55	V
V_OD	Differential output voltage	f_{O_HCSL} = 100 MHz	0.4		1.0	V
V_SS	Differential output voltage, peak to peak	f_{O_HCSL} = 100 MHz	0.8		2.0	Vpp
V_CROSS	Absolute crossing point	R_p = 49.9 Ω ±5%, f_{O_HCSL} = 100 MHz	250		550	mV
ΔV_CROSS	Relative crossing point variation	w.r.t to average crossing point, f_{O_HCSL} = 100 MHz		100		mV
dV/dt	Slew rate for rising and falling edge	Differential, at V_CROSS ±150 mV, f_{O_HCSL} = 100 MHz ⁽¹⁾	1		4	V/ns
ΔdV/dt	Slew rate matching	Single-ended, at V_CROSS ±75 mV, f_{O_HCSL} = 100 MHz ⁽¹⁾			20%
ODC	Output duty cycle	Not in PLL bypass mode	45%		55%
R_P	Parallel termination	R_p = 49.9 Ω ±5% required	45		55	Ω
L_{HCSL_100M}	Phase noise floor, single side band	f_CARRIER = 100 MHz, f_OFFSET = 10 MHz		-152		dBc/Hz

(1) PCIe test load slew rate