JAJSDY3F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fIN_Ref | Reference frequency | 1 | 250 | MHz | ||
VIH | Input high voltage | LVCMOS input buffer | 0.8 × VDDREF | V | ||
VIL | Input low voltage | LVCMOS input buffer | 0.2 × VDDREF | V | ||
VIN_DIFF | Differential input voltage swing, peak-to-peak | VDDREF = 2.5 V or 3.3 V, AC-coupled differential input buffer | 0.5 | 1.6 | V | |
VIN_DIFF | Differential input voltage swing, peak-to-peak | VDDREF = 1.8 V, AC-coupled differential input buffer | 0.5 | 1.0 | V | |
dVIN/dT | Input slew rate | 20% – 80% | 3 | V/ns | ||
IDC | Input duty cycle | 40% | 60% | |||
CIN_XOUT/FB_P | Input capacitance | No xtal active, on-chip load disabled, at 25°C | 7 | pF | ||
CIN_XIN/FB_P | Input capacitance | No xtal active, on-chip load disabled, at 25°C | 5 | pF | ||
CIN_REF | Input capacitance | at 25°C | 5 | pF |