SLLS781D February 2007 – November 2014 CDCL1810
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The CDCL1810 is a high-performance buffer that can generate 10 copies of CML clock outputs from a LVDS input. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency.
A typical application example is multi DSP chip environment. The CDCL1810 is used to buffer the common clocks to the DSP.
The CDCL1810 supports output group phase alignment, if a divider gets reprogrammed. The output group phase alignment circuit will disable all outputs after changing a single divider. The outputs are enabled after the phases are aligned. See Figure 9.
If an output gets enabled/disabled, the phase synchronization circuit will ensure that all outputs are in phase. To ensure phase alignment the outputs needs to be disabled for a short time. See Figure 10.