SLLS781D February   2007  – November 2014 CDCL1810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Added Thermal Information tableThermal Information
    5. 8.5 DC Electrical Characteristics
    6. 8.6 AC Electrical Characteristics
    7. 8.7 AC Electrical Characteristics for The SDA/SCL Interface
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable/Disable
    4. 9.4 SDA/SCL Connections Recommendations
    5. 9.5 Device Functional Modes
    6. 9.6 Programming
      1. 9.6.1 SDA/SCL Interface
        1. 9.6.1.1 SDA/SCL Bus Slave Device Address
        2. 9.6.1.2 Command Code Definition
        3. 9.6.1.3 SDA/SCL Programming Sequence
    7. 9.7 SDA/SCL Bus Configuration Command Bitmap
      1. 9.7.1 Byte 0:
      2. 9.7.2 Byte 1:
      3. 9.7.3 Byte 2:
      4. 9.7.4 Byte 3:
      5. 9.7.5 Byte 4:
      6. 9.7.6 Byte 5:
      7. 9.7.7 Byte 6:
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Distribution for Multiple TI Keystone DSPs
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

The CDCL1810 is a high-performance 10 output clock distributor. The device operates form a single 1.8-V supply. The outputs are grouped in to banks of 5 outputs each with independent frequency division ratios.

9.2 Functional Block Diagrams

bd_01_lls781.gifFigure 4. SDA/SCL Interface
bd_02_lls781.gif
Note 1: Outputs can be disabled to floating. When outputs are left floating, internal 50 Ω termination to VDD pulls both YN and YP to VDD.

9.3 Feature Description

9.3.1 Output Enable/Disable

The CDCL1810 does not require external output synchronization. Instead the device incorporates a scheme which ensures the output dividers are reset and time synchronized after every write action into the I2C programmable register space.

Flow_chart_SLLS781.gifFigure 5. Device Status Flow Chart

9.4 SDA/SCL Connections Recommendations

The serial interface inputs don’t have glitch suppression circuit. So, any noises or glitches at serial input lines may cause programming error. The serial interface lines should be routed in such a way that the lines would have minimum noise impact from the surroundings.

Figure 6 is recommended to improve the interconnections.

serial_interface_lls781.gifFigure 6. Serial Interface Connections

Lower RP resistor value (around 1 kΩ) should be chosen so that signals will have faster rise time. A capacitor can be connected to SCL line to ground which will act as a filter.

An I2C level translator will help to overcome the noises issue.

9.5 Device Functional Modes

The device is designed to operate from an input voltage supply of 1.8 V. In the default power on reset, all device outputs are enabled and the dividers P0 and P1 are set to 1.

9.6 Programming

9.6.1 SDA/SCL Interface

This section describes the SDA/SCL interface of the CDCL1810 device. The CDCL1810 operates as a slave device of the industry standard 2-pin SDA/SCL bus. It operates in the fast-mode at a bit-rate of up to 400 kbit/s and supports 7-bit addressing compatible with the popular 2-pin serial interface standard.

9.6.1.1 SDA/SCL Bus Slave Device Address

A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 ADD1 ADD0 0/1

The device address is made up of the fixed internal address, 11010 (A6:A2), and configurable external pins ADD1 (A1) and ADD0 (A0). Four different devices with addresses 1101000, 1101001, 1101010 and 1101011, can be addressed via the same SDA/SCL bus interface. The least significant bit of the address byte designates a write or read operation.

R/W Bit:

0 = write to CDCL1810 device

1 = read from CDCL1810 device

9.6.1.2 Command Code Definition

BIT DESCRIPTION
C7 1 = Byte Write / Read or Word Write / Read operation
(C6:C0) Byte Offset for Byte Write / Read and Word Write / Read operation.
COMMAND CODE for Byte Write / Read OPERATION HEX CODE C7 C6 C5 C4 C3 C2 C1 C0
byte 0 80h 1 0 0 0 0 0 0 0
byte 1 81h 1 0 0 0 0 0 0 1
byte 2 82h 1 0 0 0 0 0 1 0
byte 3 83h 1 0 0 0 0 0 1 1
byte 4 84h 1 0 0 0 0 1 0 0
byte 5 85h 1 0 0 0 0 1 0 1
byte 6 86h 1 0 0 0 0 1 1 0
COMMAND CODE for Word Write / Read OPERATION HEX CODE C7 C6 C5 C4 C3 C2 C1 C0
word 0: byte 0 and byte 1 80h 1 0 0 0 0 0 0 0
word 1: byte 1 and byte 2 81h 1 0 0 0 0 0 0 1
word 2: byte 2 and byte 3 82h 1 0 0 0 0 0 1 0
word 3: byte 3 and byte 4 83h 1 0 0 0 0 0 1 1
word 4: byte 4 and byte 5 84h 1 0 0 0 0 1 0 0
word 5: byte 5 and byte 6 85h 1 0 0 0 0 1 0 1
word 6: byte 6 and byte 7 86h 1 0 0 0 0 1 1 0

9.6.1.3 SDA/SCL Programming Sequence

tim_prog_legend_lls781.gifFigure 7. Legend for Programming Sequence

Byte WriteProgramming Sequence:

1 7 1 1 8 1 8 1 1
S Slave Address Wr A Command Code A Data Byte A P

Byte ReadProgramming Sequence:

1 7 1 1 8 1 1 7 1 1 8 1 1
S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte N P

Word WriteProgramming Sequence:

1 7 1 1 8 1 8 1 8 1 1
S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A P

Word ReadProgramming Sequence:

1 7 1 1 8 1 1 7 1 1 8 1 8 1 1
S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte A Data Byte N P

9.7 SDA/SCL Bus Configuration Command Bitmap

9.7.1 Byte 0:

BIT BIT NAME DESCRIPTION/FUNCTION TYPE POWER UP
CONDITION 		REFERENCE TO
7 MANF[7] Manufacturer reserved R
6 MANF[6] Manufacturer reserved R
5 MANF[5] Manufacturer reserved R
4 MANF[4] Manufacturer reserved R
3 MANF[3] Manufacturer reserved R
2 MANF[2] Manufacturer reserved R
1 MANF[1] Manufacturer reserved R
0 MANF[0] Manufacturer reserved R

9.7.2 Byte 1:

BIT BIT NAME DESCRIPTION/FUNCTION TYPE POWER UP
CONDITION 		REFERENCE TO
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 ENPH Phase select enable R/W 1
4 PH1[4] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4, Table 5
3 PH1[3] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4, Table 5
2 PH1[2] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4, Table 5
1 PH1[1] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4, Table 5
0 PH1[0] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 4, Table 5

9.7.3 Byte 2:

BIT BIT NAME DESCRIPTION/FUNCTION TYPE POWER UP
CONDITION		 REFERENCE TO
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 ENP1 Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are disabled R/W 1
4 RES Reserved R/W 1
3 SELP1[3] Divide ratio select for post-divider P1 R/W 0 Table 3
2 SELP1[2] Divide ratio select for post-divider P1 R/W 0 Table 3
1 SELP1[1] Divide ratio select for post-divider P1 R/W 0 Table 3
0 SELP1[0] Divide ratio select for post-divider P1 R/W 0 Table 3

9.7.4 Byte 3:

BIT BIT NAME DESCRIPTION/FUNCTION TYPE POWER UP
CONDITION		 REFERENCE TO
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 RES Reserved R/W 0
4 PH0[4] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5
3 PH0[3] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5
2 PH0[2] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5
1 PH0[1] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5
0 PH0[0] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5

9.7.5 Byte 4:

BIT BIT NAME DESCRIPTION/FUNCTION TYPE POWER UP
CONDITION		 REFERENCE TO
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 ENP0 Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are disabled R/W 1
4 RES Reserved R/W 1
3 SELP0[3] Divide ratio select for post-divider P0 R/W 0 Table 3
2 SELP0[2] Divide ratio select for post-divider P0 R/W 0 Table 3
1 SELP0[1] Divide ratio select for post-divider P0 R/W 0 Table 3
0 SELP0[0] Divide ratio select for post-divider P0 R/W 0 Table 3

9.7.6 Byte 5:

BIT BIT NAME DESCRIPTION/FUNCTION TYPE POWER UP
CONDITION		 REFERENCE TO
7 EN Chip enable; if 0 chip is in Iddq mode R/W 1
6 RES Reserved R 1
5 ENDRV9 YP[9], YN[9] enable; if 0 output is disabled R/W 1
4 ENDRV8 YP[8], YN[8] enable; if 0 output is disabled R/W 1
3 ENDRV7 YP[7], YN[7] enable; if 0 output is disabled R/W 1
2 ENDRV6 YP[6], YN[6] enable; if 0 output is disabled R/W 1
1 ENDRV5 YP[5], YN[5] enable; if 0 output is disabled R/W 1
0 ENDRV4 YP[4], YN[4] enable; if 0 output is disabled R/W 1

9.7.7 Byte 6:

BIT BIT NAME DESCRIPTION/FUNCTION TYPE POWER UP
CONDITION		 REFERENCE TO
7 ENDRV3 YP[3], YN[3] enable; if 0 output is disabled R/W 1
6 ENDRV2 YP[2], YN[2] enable; if 0 output is disabled R/W 1
5 ENDRV1 YP[1], YN[1] enable; if 0 output is disabled R/W 1
4 ENDRV0 YP[0], YN[0] enable; if 0 output is disabled R/W 1
3 RES Reserved R/W 0
2 RES Reserved R/W 0
1 RES Reserved R/W 0
0 RES Reserved R/W 0

Table 3. Divide Ratio Settings for Post-Divider P0 or P1

DIVIDE
RATIO		 SELP1[3] or
SELP0[3]		 SELP1[2] or
SELP0[2]		 SELP1[1] or
SELP0[1]		 SELP1[0] or
SELP0[0]		 NOTES
1 0 0 0 0 Default
2 0 0 0 1
4 0 0 1 0
5 0 0 1 1
8 0 1 0 0
10 0 1 0 1
16 0 1 1 0
20 0 1 1 1
32 1 0 0 0
40 1 0 0 1
80 1 0 1 0

Table 4. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80

DIVIDE
RATIO		 WITH PH0[4:0] = 00000 PHASE LEAD
(RADIAN)		 NOTES
PH1
[4] [3] [2] [1] [0]
5 X X X X X 0 Phase setting not available
10 X X X 0 X 0
X X X 1 X (2π/2)
20 X X 0 0 X 0
X X 0 1 X (2π/4)
X X 1 0 X 2(2π/4)
X X 1 1 X 3(2π/4)
40 X 0 0 0 X 0
X 0 0 1 X (2π/8)
X 0 1 0 X 2(2π/8)
X 0 1 1 X 3(2π/8)
X 1 0 0 X 4(2π/8)
X 1 0 1 X 5(2π/8)
X 1 1 0 X 6(2π/8)
X 1 1 1 X 7(2π/8)
80 0 0 0 0 X 0
0 0 0 1 X (2π/16)
0 0 1 0 X 2(2π/16)
0 0 1 1 X 3(2π/16)
0 1 0 0 X 4(2π/16)
0 1 0 1 X 5(2π/16)
0 1 1 0 X 6(2π/16)
0 1 1 1 X 7(2π/16)
1 0 0 0 X 8(2π/16)
1 0 0 1 X 9(2π/16)
1 0 1 0 X 10(2π/16)
1 0 1 1 X 11(2π/16)
1 1 0 0 X 12(2π/16)
1 1 0 1 X 13(2π/16)
1 1 1 0 X 14(2π/16)
1 1 1 1 X 15(2π/16)

Table 5. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32

DIVIDE
RATIO		 WITH PH0[4:0] = 00000 PHASE LEAD
(RADIAN)		 NOTES
PH1
[4] [3] [2] [1] [0]
1 X X X X X 0 00000: Default Phase setting not available
2 X X X X 0 0
X X X X 1 (2π/2)
4 X X X 0 0 0
X X X 0 1 (2π/4)
X X X 1 0 2(2π/4)
X X X 1 1 3(2π/4)
8 X X 0 0 0 0
X X 0 0 1 (2π/8)
X X 0 1 0 2(2π/8)
X X 0 1 1 3(2π/8)
X X 1 0 0 4(2π/8)
X X 1 0 1 5(2π/8)
X X 1 1 0 6(2π/8)
X X 1 1 1 7(2π/8)
16 X 0 0 0 0 0
X 0 0 0 1 (2π/16)
X 0 0 1 0 2(2π/16)
X 0 0 1 1 3(2π/16)
X 0 1 0 0 4(2π/16)
X 0 1 0 1 5(2π/16)
X 0 1 1 0 6(2π/16)
X 0 1 1 1 7(2π/16)
X 1 0 0 0 8(2π/16)
X 1 0 0 1 9(2π/16)
X 1 0 1 0 10(2π/16)
X 1 0 1 1 11(2π/16)
X 1 1 0 0 12(2π/16)
X 1 1 0 1 13(2π/16)
X 1 1 1 0 14(2π/16)
X 1 1 1 1 15(2π/16)
32 0 0 0 0 0 0
0 0 0 0 1 (2π/32)
0 0 0 1 0 2(2π/32)
0 0 0 1 1 3(2π/32)
0 0 1 0 0 4(2π/32)
0 0 1 0 1 5(2π/32)
0 0 1 1 0 6(2π/32)
0 0 1 1 1 7(2π/32)
0 1 0 0 0 8(2π/32)
0 1 0 0 1 9(2π/32)
0 1 0 1 0 10(2π/32)
0 1 0 1 1 11(2π/32)
0 1 1 0 0 12(2π/32)
0 1 1 0 1 13(2π/32)
0 1 1 1 0 14(2π/32)
0 1 1 1 1 15(2π/32)
1 0 0 0 0 16(2π/32)
1 0 0 0 1 17(2π/32)
1 0 0 1 0 18(2π/32)
1 0 0 1 1 19(2π/32)
1 0 1 0 0 20(2π/32)
1 0 1 0 1 21(2π/32)
1 0 1 1 0 22(2π/32)
1 0 1 1 1 23(2π/32)
1 1 0 0 0 24(2π/32)
1 1 0 0 1 25(2π/32)
1 1 0 1 0 26(2π/32)
1 1 0 1 1 27(2π/32)
1 1 1 0 0 28(2π/32)
1 1 1 0 1 29(2π/32)
1 1 1 1 0 30(2π/32)
1 1 1 1 1 31(2π/32)