SCAS895B May 2010 – February 2017 CDCLVC1102 , CDCLVC1103 , CDCLVC1104 , CDCLVC1106 , CDCLVC1108 , CDCLVC1110 , CDCLVC1112
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage | –0.5 | 4.6 | V |
VIN | Input voltage(2) | –0.5 | VDD + 0.5 | V |
VO | Output voltage(2) | –0.5 | VDD + 0.5 | V |
IIN | Input current | –20 | 20 | mA |
IO | Continuous output current | –50 | 50 | mA |
TJ | Maximum junction temperature | 125 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD | Supply voltage | 3.3-V supply | 3.0 | 3.3 | 3.6 | V |
2.5-V supply | 2.3 | 2.5 | 2.7 | |||
VIL | Low-level input voltage | VDD = 3.0 V to 3.6 V | VDD/2 – 600 | mV | ||
VDD = 2.3 V to 2.7 V | VDD/2 – 400 | |||||
VIH | High-level input voltage | VDD = 3.0 V to 3.6 V | VDD/2 + 600 | mV | ||
VDD = 2.3 V to 2.7 V | VDD/2 + 400 | |||||
Vth | Input threshold voltage | VDD = 2.3 V to 3.6 V | VDD/2 | mV | ||
tr / tf | Input slew rate | 1 | 4 | V/ns | ||
tw | Minimum pulse width at CLKIN | VDD = 3.0 V to 3.6 V | 1.8 | ns | ||
VDD = 2.3 V to 2.7 V | 2.75 | |||||
fCLK | LVCMOS clock Input Frequency | VDD = 3.0 V to 3.6 V | DC | 250 | MHz | |
VDD = 2.3 V to 2.7 V | DC | 180 | ||||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | CDCLVC1102 CDCLVC1103 CDCLVC1104 |
CDCLVC1106 | CDCLVC1108 | CDCLVC11010 | CDCLVC1112 | UNIT | |
---|---|---|---|---|---|---|---|
PW (TSSOP) | |||||||
8 PINS | 14 PINS | 16 PINS | 20 PINS | 24 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 149.4 | 112.6 | 108.4 | 83.0 | 87.9 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance (3) | 69.4 | 48.0 | 33.6 | 32.3 | 26.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
---|---|---|---|---|---|---|
OVERALL PARAMETERS FOR ALL VERSIONS | ||||||
IDD | Static device current(2) | 1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V | 6 | 10 | mA | |
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 2.7 V | 3 | 6 | ||||
IPD | Power-down current | 1G = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V or 2.7 V | 60 | µA | ||
CPD | Power dissipation capacitance per output(3) | VDD = 3.3 V; f = 10 MHz | 6 | pF | ||
VDD = 2.5 V; f = 10 MHz | 4.5 | |||||
II | Input leakage current at 1G | VI = 0 V or VDD, VDD = 3.6 V or 2.7 V | 8 | 8 | µA | |
Input leakage current at CLKIN | 25 | 25 | ||||
ROUT | Output impedance | VDD = 3.3 V | 45 | Ω | ||
VDD = 2.5 V | 60 | |||||
fOUT | Output frequency | VDD = 3 V to 3.6 V | DC | 250 | MHz | |
VDD = 2.3 V to 2.7 V | DC | 180 | ||||
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V | ||||||
VOH | High-level output voltage | VDD = 3 V, IOH = –0.1 mA | 2.9 | V | ||
VDD = 3 V, IOH = –8 mA | 2.5 | |||||
VDD = 3 V, IOH = –12 mA | 2.2 | |||||
VOL | Low-level output voltage | VDD = 3 V, IOL = 0.1 mA | 0.1 | V | ||
VDD = 3 V, IOL = 8 mA | 0.5 | |||||
VDD = 3 V, IOL = 12 mA | 0.8 | |||||
OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V | ||||||
VOH | High-level output voltage | VDD = 2.3 V, IOH = –0.1 mA | 2.2 | V | ||
VDD = 2.3 V, IOH = –8 mA | 1.7 | |||||
VOL | Low-level output voltage | VDD = 2.3 V, IOL = 0.1 mA | 0.1 | V | ||
VDD = 2.3 V, IOL = 8 mA | 0.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V | ||||||
tPLH, tPHL | Propagation delay | CLKIN to Yn | 0.8 | 2.0 | ns | |
tsk(o) | Output skew | Equal load of each output | 50 | ps | ||
tr/tf | Rise and fall time | 20%–80% (VOH - VOL) | 0.3 | 0.8 | ns | |
tDIS | Output disable time | 1G to Yn | 6 | ns | ||
tEN | Output enable time | 1G to Yn | 6 | ns | ||
tsk(p) | Pulse skew ; tPLH(Yn) – tPHL(Yn) (4) |
To be measured with input duty cycle of 50% | 180 | ps | ||
tsk(pp) | Part-to-part skew | Under equal operating conditions for two parts | 0.5 | ns | ||
tjitter | Additive jitter rms(5) | 12 kHz to 20 MHz, fOUT = 250 MHz | 100 | fs | ||
OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V | ||||||
tPLH, tPHL | Propagation delay | CLKIN to Yn | 1 | 2.6 | ns | |
tsk(o) | Output skew | Equal load of each output | 50 | ps | ||
tr/tf | Rise and fall time | 20%–80% reference point | 0.3 | 1.2 | ns | |
tDIS | Output disable time | 1G to Yn | 10 | ns | ||
tEN | Output enable time | 1G to Yn | 10 | ns | ||
tsk(p) | Pulse skew ; tPLH(Yn) – tPHL(Yn) (4) |
To be measured with input duty cycle of 50% | 220 | ps | ||
tsk(pp) | Part-to-part skew | Under equal operating conditions for two parts | 1.2 | ns | ||
tjitter | Additive jitter rms(5) | 12 kHz to 20 MHz, fOUT = 180 MHz | 350 | fs |