SCAS841D February   2007  – December 2016 CDCLVD110A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: LVDS
    7. 6.7 Jitter Characteristics
    8. 6.8 Control Register Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Information
      2. 8.4.2 LVDS Receiver Input Termination
      3. 8.4.3 Input Termination
      4. 8.4.4 LVDS Output Termination
      5. 8.4.5 Control Inputs Termination
    5. 8.5 Programming
      1. 8.5.1 Specification of Control Register
        1. 8.5.1.1 Programmable Mode (EN = 1)
        2. 8.5.1.2 Standard Mode (EN = 0)
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

CDCLVD110A pmi_wf_cas684.gif
A. Output skew, tsk(o), is calculated as the greater of:
– The difference between the fastest and the slowest tPLHn (n = 1, 2,...10)
– The difference between the fastest and the slowest tPHLn (n = 1, 2,...10)
B. Part-to-part skew, tsk(pp), is calculated as the greater of:
– The difference between the fastest and the slowest tPLHn (n = 1, 2,...10) across multiple devices
– The difference between the fastest and the slowest tPHLn (n = 1, 2,...10) across multiple devices
C. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tPHL) and the low-to-high (tPLH) propagation delays when a single switching input causes one or more outputs to switch,
tsk(p) = | tPHL – tPLH |. Pulse skew is sometimes referred to as pulse-width distortion or duty-cycle skew.
Figure 2. Waveforms for Calculation of tsk(o) and tsk(pp)
CDCLVD110A pmi_tst_cas684.gif Figure 3. Test Criteria for fclk, Duty Cycle, tr, tf, VOD
CDCLVD110A DC_output_cas897.gif Figure 4. LVDS Output DC Configuration During Device Test
CDCLVD110A AC_output_cas897.gif Figure 5. LVDS Output AC Configuration During Device Test
CDCLVD110A LVCMOS_tst_cas898.gif Figure 6. DC-Coupled LVCMOS Input During Device Test
CDCLVD110A rise_fall_tim_cas899.gif Figure 7. Output Voltage and Rise/Fall Time