SCAS841D February   2007  – December 2016 CDCLVD110A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: LVDS
    7. 6.7 Jitter Characteristics
    8. 6.8 Control Register Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Information
      2. 8.4.2 LVDS Receiver Input Termination
      3. 8.4.3 Input Termination
      4. 8.4.4 LVDS Output Termination
      5. 8.4.5 Control Inputs Termination
    5. 8.5 Programming
      1. 8.5.1 Specification of Control Register
        1. 8.5.1.1 Programmable Mode (EN = 1)
        2. 8.5.1.2 Standard Mode (EN = 0)
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

VF or RHB Package
32-Pin LQFP or VQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CK 1 I Control register input clock, features a 120-kΩ pullup resistor
CLK0 3 I True differential input, LVDS
CLK0 4 I Complementary differential input, LVDS
CLK1 6 I True differential input, LVDS
CLK1 7 I Complementary differential input, LVDS
EN 8 I Control enable (for programmability), features a 120-kΩ pulldown resistor, input
PowerPAD™ — I/O The PowerPAD of the VQFN package is thermally connected to the die to improve the heat transfer out of the package. This pad is connected to GND.
Q[9:0] 11, 13, 15, 18, 20,
22, 24, 27, 29, 31		 O Clock outputs, these outputs provide low-skew copies of CLKIN
Q[9:0] 10, 12, 14, 17, 19,
21,23, 26, 28, 30		 O Complementary clock outputs, these outputs provide low-skew copies of CLKIN
SI 2 I Control register serial input/CLK Select, features a 120-kΩ pulldown resistor
VBB 5 O Reference voltage output
VDD 16, 32 — Supply voltage
VSS 9, 25 — Device ground