SCAS897A July   2010  – October 2016 CDCLVD1213

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVD1213 is a low additive jitter universal to LVDS fan-out buffer with an integrated frequency divider on one output. The small package, low output skew, and low additive jitter make for a flexible device in demanding applications.

9.2 Typical Application

CDCLVD1213 CDCLVD12xx_app_blockdiagram.gif Figure 15. Fan-Out Buffer for Line Card Application

9.2.1 Design Requirements

The CDCLVD1213 shown in Figure 15 is configured with a 156.25-MHz LVDS clock from the backplane as its input frequency. The LVDS clock is AC-coupled. A resistor divider (and a 0.1-µF capacitor to reduce noise) is used to set the bias voltage correctly at the VT pin. The configuration example is driving 4 LVDS receivers in a line card application with the following properties:

  • The PHY device is capable of DC-coupling with an LVDS driver such as the CDCLVD1213. This PHY device features internal termination so no additional components are required for proper operation.
  • The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as the CDCLVD1213. Again, no additional components are required.
  • The FPGA requires external AC-coupling, but has internal termination. 0.1-µF capacitors are placed to provide AC-coupling.
  • The CPU on output QD is internally terminated, and requires only external AC-coupling capacitors. The DIV pin is pulled to ground with a 100-Ω resistor to set the frequency divider to 1 so that the CPU clock frequency is also 156.25 MHz.

9.2.2 Detailed Design Procedure

See Input Termination for proper input terminations, dependent on single-ended or differential inputs.

See LVDS Output Termination for output termination schemes depending on the receiver application.

Unused outputs can be left floating.

In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power supply filtering and bypassing is critical for low-noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in Low-Additive Jitter, Four-LVDS-Outputs Clock Buffer With Divider EVM (SCAU044).

9.2.3 Application Curves

The CDCLVD12xx's low additive noise is shown in this line card application. The low noise 156.25-MHz source with 67-fs RMS jitter drives the CDCLVD12xx, resulting in 80-fs RMS when integrated from 12 kHz to 20 MHz. The resultant additive jitter is a low 44-fs RMS for this configuration.

CDCLVD1213 SCAS898_application_source.gif
Reference signal is low-noise Rohde and Schwarz SMA100A
Figure 16. CDCLVD12xx Reference Phase Noise,
67-fs RMS (12 kHz to 20 MHz)
CDCLVD1213 SCAS898_application_output.gif
Figure 17. CDCLVD12xx Output Phase Noise,
80-fs RMS (12 kHz to 20 MHz)